Analysis of the quasi-saturation behavior considering the drain-to-source voltage and cell-spacing effects for a vertical DMOS power transistor

Solid State Electronics

Volumn 36, Issue 1, 1993, Pages 85-91

  Lou, K H ^a   Liu, C M ^a   Kuo, J B ^a  

^a NATIONAL TAIWAN UNIVERSITY   (Taiwan)

Author keywords

[No Author keywords available]

Indexed keywords

MOS DEVICES; SEMICONDUCTOR DEVICE MODELS;

DMOS POWER TRANSISTORS; DMOS TRANSISTORS; DRAIN-TO-SOURCE VOLTAGE; POWER TRANSISTORS;

FIELD EFFECT TRANSISTORS;

EID: 0027201356     PISSN: 00381101     EISSN: None     Source Type: Journal    
DOI: 10.1016/0038-1101(93)90072-X     Document Type: Article

References (9)

1. Study of the quasi-saturation effect in VDMOS transistors
2. A better understanding of CMOS latch-up
3. PISCES 2: Poisson and Continuity Equation Solver