Series Resistance of Self-Aligned Silicided Source/Drain Structure

IEEE Transactions on Electron Devices

Volumn 40, Issue 1, 1993, Pages 197-206

  Chen, Mao Chieh ^b  

^a INDUSTRIAL TECHNOLOGY RESEARCH INSTITUTE   (Taiwan)

^b NATIONAL CHIAO TUNG UNIVERSITY   (Taiwan)

Author keywords

[No Author keywords available]

Indexed keywords

COMPUTER SIMULATION; ELECTRIC RESISTANCE MEASUREMENT; SEMICONDUCTING SILICON; SEMICONDUCTOR DEVICE MODELS; SEMICONDUCTOR JUNCTIONS;

RECESSED CONTACT INTERFACE; SELF-ALIGNED SILICIDED SOURCE/DRAIN STRUCTURE; SERIES RESISTANCE; SHORT-CHANNEL MOSFETS; TWO-DIMENSIONAL SIMULATION;

MOSFET DEVICES;

EID: 0027187365     PISSN: 00189383     EISSN: 15579646     Source Type: Journal    
DOI: 10.1109/16.249444     Document Type: Article

References (33)

1. Y. El-Mansy, “MOS device and technology constraints in VLSI,” IEEE Trans. Electron Devices, vol. ED-29, 567, 1982.
2. H. Shichijo, “A re-examination of practical performance limits of scaled n-channel and p-channel MOS devices for VLSI,” Solid-State Electron., vol. 26, p. 969, 1983.
3. A. Yagi and J. Frey, “Effects of injection resistance on the performance of very-short-channel MOSFET’s,” IEEE Trans. Electron Devices, vol. ED-31, p. 1804, 1984.
4. K. K. Ng and W. T. Lynch, “Analysis of the gate-voltage-dependent series resistance of MOSFET’s,” IEEE Trans. Electron Devices, vol. ED-33, p. 965, 1986.
5. K. K. Ng and W. T. Lynch, “The impact of intrinsic series resistance on MOSFET scaling,” IEEE Trans. Electron Devices, vol. ED-34, 503, 1987.
6. M. C. Jeng, J. E. Chung, P. K. Ko, and C. Hu, “The effect of source/ drain resistance on deep submicrometer device performance,” IEEE Trans. Electron Devices, vol. 37, 2408, 1990.
7. B. Davari, W. H. Chang, and M. R. Wordeman, C. S. Oh, Y. Taur, K. E. Petrillo, D. Moy, J. J. Bucchignano, H. Y. Ng, M. G. Rosen-field, F. J. Hohn, and M. D. Rodriguez, “A high performance 0.25 μ m CMOS technology,” in IEDM Tech. Dig., 1988, p. 56.
8. M. Kinugawa, M. Kakuma, S. Yokogawa, and K. Hashimoto, “Sub-micron MLDD NMOSFET for 5 V operation,” in Proc. VLSI Symp., 1985, p. 116.
9. T. Y. Huang, W. W. Yao, R. A. Martin, A. G. Lewis, M. Koyanagi, and J. Y. Chen, “A novel submicron LDD transistor with inverse-T gate structure,” in IEDM Tech. Dig., 1986, p. 742.
10. R. Izawa, T. Kure, S. Iijima, and E. Takeda, “The impact of gate-drain overlapped LDD (GOLD) for deep submicron VLSI’s,” in IEDM Tech. Dig., 1987, p. 38.
11. T. Hori and K. Kurimoto, “A new MOSFET with large-tilt-angle implantation drain (LATID) structure,” IEEE Electron Device Lett., vol. 9, p. 300, 1988.
12. T. N. Buti, S. Ogura, N. Rovedo, K. Tobimatsu, and C. F. Codella, “Asymmetrical halo source GOLD drain (HS-GOLD) deep sub-half micron n-MOSFET design for reliability and performance,” in IEDM Tech. Dig., 1989, p. 617.
13. D. B. Scott, W. R. Hunter, and H. Shichijo, “A transmission line model for silicided diffusions: impact on the performance of VLSI circuits,” IEEE Trans. Electron Devices, vol. ED-29, p. 651, 1982.
14. +implantsinto crystalline and amorphous silicon,” J. Appl. Phys., vol. 54, p. 6879, 1983.
15. W. J. M. J. Josquin, P. R. Boudewijn, and Y. Tamminga, “Effectiveness of polycrystalline silicon diffusion sources,” Appl. Phys. Lett., vol. 43, p. 960, 1983.
16. P. G. Carey, T. W. Sigmon, R. L. Press, and T. S. Fahlen, “Ultra-shallow high-concentration boron profiles for CMOS processing,” IEEE Electron Device Lett., vol. EDL-6, p. 241, 1985.
17. +/n junctions by doped silicide technology,” in IEDM Tech. Dig., 1985, 407.
18. +-n junctions for CMOS technology” IEEE Electron Device Lett., vol. EDL-8, p. 96, 1987.
19. M. Miyake, T. Kobayashi, and Y. Okazaki, “Subquarter-micrometer gate-length p-channel and n-channel MOSFET’s with extremely shallow source-drain junctions,” IEEE Trans. Electron Devices, vol. 36, p. 392, 1989.
20. T. Shibata, K. Hieda, M. Sato, M. Konaka, R. L. M. Dang, and H. Iizuka, “An optimally designed process for submicron MOSFETs,” in IEDM Tech. Dig., 1981, p. 647.
21. S. P. Murarka, “Self-aligned silicides or metals for very large scale integrated circuit applications,” J. Vac. Sci. Technol., vol. B4, p. 1325, 1986.
22. C. K. Lau, Y. C. See, D. B. Scott, J. M. Bridge, R. L. M. Dang, and H. Iizuka, “Titanium disilicide self-aligned source-drain and gate technology,” in IEDM Tech. Dig., 1982, p. 714.
23. 2interconnection and contact technology for VLSI applications,” IEEE Trans. Electron Devices, vol. ED-34, p. 554, 1987.
24. B. Y. Tsui, W. L. Yang, T. F. Lei, C. L. Lee, and M. C. Chen, “Underestimation of recessed metal/silicon contact resistance measured by the cross bridge Kelvin resistor structure,” to be published.
25. D. A. Antoniadis, A. G. Gonzalez, and R. W. Dutton, “Boron in near-intrinsic < 100> and <111> silicon under inert and oxidizing ambient-diffusion and segregation,” J. Electrochem. Soc., vol. 125, p. 813, 1978.
26. G. Baccarani and P. Ostoja, “Electron mobility empirically related to the phosphorus concentration in silicon,” Solid-State Electron., vol. 18, p. 579, 1975.
27. J. B. Lasky, J. S. Nakos, O. J. Cain, and P. J. Geiss, “Comparison of transformation to low-resistivity phase and agglomeration on TiSi 2 and CoSi 2,” IEEE Trans. Electron Devices, vol. 38, p. 263, 1991.
28. H. H. Berger, “Models for contacts to planar devices,” Solid-State Electron., vol. 15, p. 145, 1972.
29. A. H. Perera and J. P. Krusius, “Ultimate CMOS density limits: measured source drain resistance in ultra small devices,” in IEDM Tech. Dig., 1989, p. 625.
30. Y. Taur, J. Y. C. Sun, D. Moy, L. K. Wang, B. Davari, S. P. Klepner, and C. Y. Ting, “Source-drain contact resistance in CMOS with self-aligned TiSi 2,” IEEE Trans. Electron Devices, vol. ED-34, p. 575, 1987.
31. S. S. Wong, D. R. Broadbury, and K. Y. Chiu, “Elevated source/ drain MOSFET,” in IEDM Tech. Dig., 1984, p. 634.
32. J. R. Pfiester, R. D. Sivan, H. M. Liaw, C. A. Seelbach, and C. D. Gunderson, “A self-aligned elevated source/drain MOSFET,” IEEE Electron Device Lett., vol. 11, p. 365, 1990.
33. K. K. Ng and R. Liu, “On the calculation of specific contact resistivity on < 100> Si,” IEEE Trans. Electron Devices, vol. 37, p. 1535, 1990.