|
|
|
Volumn 1, Issue , 1993, Pages 627-630
|
|
Efficient FIR filter architecture
|
|
Author keywords
[No Author keywords available]
|
|
Indexed keywords
ADDERS;
COMPUTATIONAL COMPLEXITY;
DIGITAL ARITHMETIC;
DIGITAL SIGNAL PROCESSING;
ELECTRIC NETWORK ANALYSIS;
FIR FILTERS;
FLIP FLOP CIRCUITS;
PARALLEL PROCESSING SYSTEMS;
SAMPLED DATA CONTROL SYSTEMS;
SAMPLING;
SCHEMATIC DIAGRAMS;
VLSI CIRCUITS;
BIT LEVEL PARALLELISM;
FIELD PROGRAMMABLE GATE ARRAYS;
FILTER TAPS;
FULL ADDERS;
INTERMEDIATE WORDLENGTH;
LATCHES;
SAMPLING RATES;
SPARSITY;
WORD LEVEL PARALLELISM;
DIGITAL FILTERS;
|
|
EID: 0027167333
PISSN: 02714310
EISSN: None
Source Type: Conference Proceeding
DOI: None Document Type: Conference Paper |
|
Times cited : (18)
|
|
References (19)
|
