Clock recovery circuits with instantaneous locking

Electronics Letters

Volumn 28, Issue 23, 1992, Pages 2127-2130

  Banu, M ^a   Dunlop, A E ^a  

^a LUCENT TECHNOLOGIES   (United States)

Author keywords

Clock recovery circuits

Indexed keywords

CMOS INTEGRATED CIRCUITS; CODES (SYMBOLS); PHASE LOCKED LOOPS; SIMULATION;

BANDWIDTH WASTING MANCHESTER LINE CODING; CLOCK RECOVERY CIRCUITS; ZERO TO ZERO LINE CODING;

INTEGRATED CIRCUITS;

EID: 0027112889     PISSN: 00135194     EISSN: None     Source Type: Journal    
DOI: 10.1049/el:19921366     Document Type: Article

References (3)

1. DORROS, I., SIPRESS, J. M., and WALDHAUER, F. D.: ‘An experimental 224Mb/s digital repeatered line’, Bell Syst. Tech. J., September 1966, pp. 993-1043
2. MAIONE, T. L., SELL, D. D., and WOLAVER, D. H.: ‘Practical 45-Mb/s regenerator for lightwave transmission’, Bell Syst. Tech. J., July-August 1978, pp.1837-1879
3. BELL, A. G., and BORRIELLO, G.: ‘A single chip NMOS ethernet controller’. Digest of Technical Papers, IEEE International Solid-State Circuits Conference, New York, February 1983, pp. 70-71