Input and output queueing atm switch architecture with spatial and temporal slot reservation control

Electronics Letters

Volumn 28, Issue 1, 1992, Pages 22-24

  Obara, H ^a   Okamoto, S ^a   Hamazumi, Y ^a  

^a NTT CORPORATION   (Japan)

Author keywords

Digital communication systems; Integrated services digital network; Switching

Indexed keywords

DIGITAL COMMUNICATION SYSTEMS; PROBABILITY--QUEUEING THEORY;

ATM SWITCH ARCHITECTURE; SLOT RESERVATION CONTROL; SPACE DIVISION SWITCHES;

SWITCHING SYSTEMS;

EID: 0027107068     PISSN: 00135194     EISSN: None     Source Type: Journal    
DOI: 10.1049/el:19920014     Document Type: Article

References (5)

1. Obara, H., and Yasushi, T.I., ‘High speed transport processor for broadband burst transport system’. Proc. IEEE Int. Conf. on Communications, Philadelphia, 1988, pp. 922–927
2. Obara, H., Sasagawa, M., and Tokizawa, L. ‘An ATM crossconnect system for broadband transport networks based on virtual path concept’. Proc. IEEE Int. Conf. on Communications, Atlanta, 1990, pp. 839–843
3. Tokizawa, I., and Sato, K.: ‘Broadband transport techniques based on virtual path’. Proc. IEEE Global Telecommunications Conf., San Diego, 1990, pp. 1269–1273
4. Obara, H.: ‘Optimum architecture for input queueing ATM switches’. Electron. Lett., 1991, 27, (7), pp. 555–556
5. Eng, K. Y., Karol, M. J., and Chih-Lin, I.: ‘A modulator broadband (ATM) switch architecture with optimum performance’. Proc. 13th Int. Switching Symp., Vol. IV, Stockholm, 1990, pp. 1–6