Formal method for self-timed design

Volumn , Issue , 1992, Pages 197-201

  Kishinevsky, M A ^a   Kondratyev, A Y ^a   Taubin, A R ^a  

^a R&D Coop Trassa ^*  (Russian Federation)

Author keywords

[No Author keywords available]

Indexed keywords

ALGORITHMS; BOOLEAN FUNCTIONS; FORMAL LOGIC; INTEGRATED CIRCUIT LAYOUT; POLYNOMIALS; SEQUENTIAL MACHINES;

CHANGE DIAGRAMS; COMPACT EVENT MODEL; CONCURRENCY SEMANTICS; FORMAL METHOD; SELF-TIMED CIRCUIT DESIGN;

VLSI CIRCUITS;

EID: 0027101294     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (9)