Methods for reducing events in sequential circuit fault simulation

1991 IEEE International Conference on Computer-Aided Design Digest of Technical Papers

Volumn , Issue , 1992, Pages 546-549

  Rudnick, Elizabeth M ^a   Niermann, Thomas M ^a   Patel, Janak H ^a  

^a UNIVERSITY OF ILLINOIS AT URBANA CHAMPAIGN   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

ALGORITHMS; COMPUTER AIDED LOGIC DESIGN; COMPUTER SIMULATION;

BENCHMARKS; FAULT SIMULATION;

SEQUENTIAL CIRCUITS;

EID: 0027099470     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (9)