Two-dimensional layout synthesis for large-scale CMOS circuits

1991 IEEE International Conference on Computer-Aided Design Digest of Technical Papers

Volumn , Issue , 1992, Pages 490-493

  Tani, Katsunori ^a   Izumi, Kyoichi ^a   Kashimura, Masahiko ^a   Matsuda, Tsuneo ^a   Fujii, Takashi ^a  

^a NEC CORPORATION   (Japan)

Author keywords

[No Author keywords available]

Indexed keywords

ALGORITHMS; COMPUTER AIDED LOGIC DESIGN; INTEGRATED CIRCUIT LAYOUT; TRANSISTORS;

BENCHMARKS;

CMOS INTEGRATED CIRCUITS;

EID: 0027084256     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (17)