On variable ordering of binary decision diagrams for the application of multi-level logic synthesis

Volumn , Issue , 1992, Pages 50-54

  Fujita, Masahiro ^a   Matsunaga, Yusuke ^a   Kakuda, Taeko ^a  

^a FUJITSU LABORATORIES LTD   (Japan)

Author keywords

[No Author keywords available]

Indexed keywords

ALGORITHMS; BINARY SEQUENCES; BOOLEAN FUNCTIONS; FLOWCHARTING; LOGIC PROGRAMMING; MINIMIZATION OF SWITCHING NETS;

BINARY DECISION DIAGRAM (BDD); MULTILEVEL LOGIC MINIMIZATION PROGRAMS; TWO LEVEL CIRCUITS;

LOGIC DESIGN;

EID: 0027047925     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (14)