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Volumn 39, Issue 12, 1992, Pages 2733-2739

A Fully Complementary BiCMOS Technology for Sub-Half-Micrometer Microprocessor Applications

Author keywords

[No Author keywords available]

Indexed keywords

BIPOLAR TRANSISTORS; MICROPROCESSOR CHIPS; SCHOTTKY BARRIER DIODES;

EID: 0027004073     PISSN: 00189383     EISSN: 15579646     Source Type: Journal    
DOI: 10.1109/16.168754     Document Type: Article
Times cited : (7)

References (13)
  • 2
    • 84941607697 scopus 로고
    • A dual-poly (N +/P+) gate, Ti-SALICIDE, double-metal technology for submicron CMOS ASIC and logic applications
    • S. W. Sun, M. Swenson, J. R. Yeargain, C-O. Lee, C. Swift, J. R. Pfiester, W. Bibeau, and W. Atwell, “A dual-poly (N +/P+) gate, Ti-SALICIDE, double-metal technology for submicron CMOS ASIC and logic applications,” in Proc. IEEE CICC, 1989, pp. 18.7.118.7.4.
    • (1989) Proc. IEEE CICC , pp. 18.7.1-18.7.4
    • Sun, S.W.1    Swenson, M.2    Yeargain, J.R.3    Lee, C.O.4    Swift, C.5    Pfiester, J.R.6    Bibeau, W.7    Atwell, W.8
  • 8
    • 0024863136 scopus 로고
    • Oxide charge trapping and HCI susceptibility of a submicron CMOS dual-poly (N +/P +) gate technology
    • S. W. Sun, K-Y. Fu, C. T. Swift, and J. R. Yeargain, “Oxide charge trapping and HCI susceptibility of a submicron CMOS dual-poly (N +/P +) gate technology,” in Proc. IEEE IRPS, 1989, pp. 183-188.
    • (1989) Proc. IEEE IRPS , pp. 183-188
    • Sun, S.W.1    Fu, K.Y.2    Swift, C.T.3    Yeargain, J.R.4
  • 10
    • 84941607698 scopus 로고
    • Field-plated high gain lateral bipolar transistor in standard CMOS process for BiNMOS application
    • K. K. Au, P. G. Y. Tsui, Y. S. Kim, K. K. Diogu, M. L. Kosty, and C. M. Palmer, “Field-plated high gain lateral bipolar transistor in standard CMOS process for BiNMOS application,” in Proc. IEEE CICC, 1990, pp. 18.5.1-18.5.4.
    • (1990) Proc. IEEE CICC , pp. 18.5.1-18.5.4
    • Au, K.K.1    Tsui, P.G.Y.2    Kim, Y.S.3    Diogu, K.K.4    Kosty, M.L.5    Palmer, C.M.6
  • 11
    • 84870038042 scopus 로고
    • A modular 0.5-micron BiCMOS technology for low voltage logic applications
    • P. G. Y. Tsui, S. W. Sun, J. R. Yeargain, and B. Pappert, “A modular 0.5-micron BiCMOS technology for low voltage logic applications,” in Proc. IEEE CICC, 1992, pp. 9.4.1-9.4.4.
    • (1992) Proc. IEEE CICC , pp. 9.4.1-9.4.4
    • Tsui, P.G.Y.1    Sun, S.W.2    Yeargain, J.R.3    Pappert, B.4
  • 13
    • 0026257211 scopus 로고
    • Merged BiCMOS logic to extend the CMOS/BiCMOS performance crossover below 2.5-V supply
    • Nov.
    • R. B. Ritts, P. A. Raje, J. D. Plummer, K. C. Saraswat, and K. M. Cham, “Merged BiCMOS logic to extend the CMOS/BiCMOS performance crossover below 2.5-V supply,” IEEE J. Solid-State Circuits, vol. 26, no. 11, pp. 1606-1614, Nov. 1991.
    • (1991) IEEE J. Solid-State Circuits , vol.26 , Issue.11 , pp. 1606-1614
    • Ritts, R.B.1    Raje, P.A.2    Plummer, J.D.3    Saraswat, K.C.4    Cham, K.M.5


* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.