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Volumn 27, Issue 12, 1992, Pages 1916-1926

Design Techniques for High-Speed, High-Resolution Comparators

Author keywords

[No Author keywords available]

Indexed keywords

AMPLIFIERS (ELECTRONIC); ANALOG TO DIGITAL CONVERSION; CMOS INTEGRATED CIRCUITS; COMPUTER SIMULATION; ELECTRIC WAVEFORMS; TRANSIENTS; VLSI CIRCUITS;

EID: 0026996006     PISSN: 00189200     EISSN: 1558173X     Source Type: Journal    
DOI: 10.1109/4.173122     Document Type: Article
Times cited : (393)

References (9)
  • 1
    • 0005259274 scopus 로고
    • Low-level MOS transistor amplifier using storage techniques
    • Feb.
    • R. Poujois et al., “Low-level MOS transistor amplifier using storage techniques,” in ISSCC Dig. Tech. Papers, Feb. 1973, pp. 152–153.
    • (1973) ISSCC Dig. Tech. Papers , pp. 152-153
    • Poujois, R.1
  • 2
    • 0024648085 scopus 로고
    • A 10-bit 5-Msample/s CMOS two-step flash ADC
    • Apr.
    • J. Doemberg, P. R. Gray, and D. A. Hodges, “A 10-bit 5-Msample/s CMOS two-step flash ADC,” IEEE J. Solid-State Circuits, vol. 24, pp. 241–249, Apr. 1989.
    • (1989) IEEE J. Solid-State Circuits , vol.24 , pp. 241-249
    • Doemberg, J.1    Gray, P.R.2    Hodges, D.A.3
  • 3
    • 0020243830 scopus 로고
    • A precision variable-supply CMOS comparator
    • Dec.
    • D. J. Allstot, “A precision variable-supply CMOS comparator,” IEEE J. Solid-State Circuits, vol. SC-17, pp. 1080–1087, Dec. 1982.
    • (1982) IEEE J. Solid-State Circuits , vol.SC-17 , pp. 1080-1087
    • Allstot, D.J.1
  • 4
    • 0024887001 scopus 로고
    • A multistep ADC family with efficient architecture
    • Feb.
    • S. Chin, M. K. Mayes, and R. Filippi, “A multistep ADC family with efficient architecture,” in ISSCC Dig. Tech. Papers, Feb. 1989, pp. 16–17.
    • (1989) ISSCC Dig. Tech. Papers , pp. 16-17
    • Chin, S.1    Mayes, M.K.2    Filippi, R.3
  • 5
    • 0019702024 scopus 로고
    • Amplifier techniques for combining low noise, precision, and high-speed performance
    • Dec.
    • G. Erdi, “Amplifier techniques for combining low noise, precision, and high-speed performance,” IEEE J. Solid-State Circuits, vol. SC-16, pp. 653–661, Dec. 1981.
    • (1981) IEEE J. Solid-State Circuits , vol.SC-16 , pp. 653-661
    • Erdi, G.1
  • 6
    • 0025384824 scopus 로고
    • An 8-bit 200-MHz BiCMOS comparator
    • Feb.
    • P. J. Lim and B. A. Wooley, “An 8-bit 200-MHz BiCMOS comparator,” IEEE J. Solid-State Circuits, vol. 25, pp. 192–199, Feb. 1990.
    • (1990) IEEE J. Solid-State Circuits , vol.25 , pp. 192-199
    • Lim, P.J.1    Wooley, B.A.2
  • 7
    • 84933459323 scopus 로고
    • BiCMOS technology overview
    • Center for Integrated Systems, Stanford Univ., Stanford, CA, Sept.
    • J. Shott, C. Knorr, and M. Prisbe, “BiCMOS technology overview,” Stanford BiCMOS Project Tech. Rep., Center for Integrated Systems, Stanford Univ., Stanford, CA, Sept. 1990.
    • (1990) Stanford BiCMOS Project Tech. Rep.
    • Shott, J.1    Knorr, C.2    Prisbe, M.3
  • 8
    • 0024906247 scopus 로고
    • A single-poly CMOS process merging analog capacitors, bipolar and EPROM devices
    • May
    • T.-I. Liou et al., “A single-poly CMOS process merging analog capacitors, bipolar and EPROM devices,” in Proc. VLSI Tech. Symp., May 1989, pp. 37–38.
    • (1989) Proc. VLSI Tech. Symp. , pp. 37-38
    • Liou, T.I.1
  • 9
    • 0024125241 scopus 로고
    • A 100-MHz pipelined CMOS comparator
    • Dec.
    • J. T. Wu and B. A. Wooley, “A 100-MHz pipelined CMOS comparator,” IEEE J. Solid-State Circuits, vol. 23, pp. 1379–1385, Dec. 1988.
    • (1988) IEEE J. Solid-State Circuits , vol.23 , pp. 1379-1385
    • Wu, J.T.1    Wooley, B.A.2


* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.