A 12-b 5-MSample/s Two-Step CMOS A/D Converter

IEEE Journal of Solid-State Circuits

Volumn 27, Issue 12, 1992, Pages 1667-1678

  Wooley, Bruce A ^b  

^a LUCENT TECHNOLOGIES   (United States)

^b STANFORD UNIVERSITY   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

CAPACITORS; CMOS INTEGRATED CIRCUITS; COMPARATOR CIRCUITS; EQUIVALENT CIRCUITS; REDUNDANCY;

HALF-FLASH ARCHITECTURE; SUBTRACTOR NONLINEARITY; TWO-STEP CMOS A/D CONVERTER; TWO-STEP FLASH TOPOLOGY;

ANALOG TO DIGITAL CONVERSION;

EID: 0026992735     PISSN: 00189200     EISSN: 1558173X     Source Type: Journal    
DOI: 10.1109/4.173092     Document Type: Article

References (14)

1. D. A. Kerth, N. S. Sooch, and E. J. Swanson, “A 12-bit 1-MHz two-step flash ADC,” IEEE J. Solid-State Circuits, vol. 24, pp. 250–255, Apr. 1989.
2. J. Doemberg, P. R. Gray, and D. A. Hodges, “A 10-bit 5-Msample/s CMOS two-step flash ADC,” IEEE J. Solid-State Circuits, vol. 24, pp. 241–249, Apr. 1989.
3. J. L. McCreary and P. R. Gray, “All-MOS charge redistribution analog-to-digital conversion techniques—Part I,” IEEE J. Solid-State Circuits, vol. SC-10, pp. 371–379, Dec. 1975.
4. R. E. Suarez, P. R. Gray, and D. A. Hodges, “All-MOS charge redistribution analog-to-digital conversion techniques—Part II,” IEEE J. Solid-State Circuits, vol. SC-10, pp. 379–385, Dec. 1975.
5. B. S. Song, S. H. Lee, and M. F. Tompsett, “A 10-b 15-MHz CMOS recycling two-step A/D converter,” IEEE J. Solid-State Circuits., vol. 25, pp. 1328–1338, Dec. 1990.
6. A. G. F. Dingwall, “Monolithic expandable 6 bit 20 MHz CMOS/SOS A/D converter,” IEEEJ. Circuits, vol. SC-14, pp. 926–932, Dec. 1979.
7. B. Razavi and B. A. Wooley, “Design techniques for high-speed, high-resolution comparators,” this issue, pp. 1916–1926.
8. K. Tsugaru et al., “A 10-bit 40MHz ADC using 0.8 um BiCMOS technology,” in Proc. Bipolar Circuits and Technol. Meet., Sept. 1989, pp. 48–51.
9. S. H. Lewis and P. R. Gray, “A pipelined 5-Msample/s 9-bit analog-to-digital converter,” IEEE J. Solid-State Circuits, vol. SC-22, pp. 954–961, Dec. 1987.
10. O. A. Homa, “A 150 Mbps A/D and D/A conversion system,” COMSAT Tech. Rev., vol. 2, pp. 39–72, Spring 1972.
11. T-I. Liou et al., “A single-poly CMOS process merging analog capacitors, bipolar and EPROM devices,” in Proc. VLSI Tech. Symp., May 1989, pp. 37–38.
12. J. Doemberg et al., “Full-speed testing of A/D converters,” IEEE J. Solid-State Circuits, vol. SC-19, pp. 820–827, Dec. 1984.
13. B. Boser et al., “Simulating and testing oversampled analog-to-digital converters,” IEEE Trans. Computer-Aided Design, vol. 7, pp. 668-674, June 1988.
14. L. Williams et al., “MIDAS User Manual, Version 2.0,” Integrated Circuits Lab., Stanford Univ., Stanford, CA, Aug. 1989.