PAR-APLAC: Parallel circuit analysis and optimization

European Design Automation Conference

Volumn , Issue , 1992, Pages 584-589

  Pajarre, Eero ^a   Ritoniemi, Tapani ^a   Tenhunen, Hannu ^a  

^a TAMPERE UNIVERSITY OF TECHNOLOGY   (Finland)

Author keywords

[No Author keywords available]

Indexed keywords

COMPUTER AIDED ANALYSIS; COMPUTER SIMULATION; COMPUTER SOFTWARE; COMPUTER WORKSTATIONS; EFFICIENCY; ELECTRIC NETWORK ANALYSIS; OBJECT ORIENTED PROGRAMMING; OPTIMIZATION; PARALLEL PROCESSING SYSTEMS;

OBJECT ORIENTED ANALOG CIRCUIT SIMULATOR AND DESIGN TOOL; PARALLEL CIRCUITS;

COMPUTER CIRCUITS;

EID: 0026992223     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (12)