Single-Precision Multiplier with Reduced Circuit Complexity for Signal Processing Applications

IEEE Transactions on Computers

Volumn 41, Issue 10, 1992, Pages 1333-1336

  Lim, Y C ^a  

^a NATIONAL UNIVERSITY OF SINGAPORE   (Singapore)

Author keywords

[No Author keywords available]

Indexed keywords

DIGITAL SIGNAL PROCESSING; LOGIC CIRCUITS;

CIRCUIT COMPLEXITY; MULTIPLICATION; SINGLE PRECISION MULTIPLIERS;

DIGITAL ARITHMETIC;

EID: 0026941356     PISSN: 00189340     EISSN: None     Source Type: Journal    
DOI: 10.1109/12.166611     Document Type: Article

References (8)

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3. A. V. Oppenheim and R. W. Schafer, Digital Signal Processing. Englewood Cliffs, N J: Prentice-Hall, 1975.
4. L. R. Rabiner and B. Gold, Theory and Application of Digital Signal Processing. Englewood Cliffs, NJ: Prentice-Hall, 1975.
5. S. Nakamura and K. Y. Chu, “A single chip parallel multiplier by MOS technology,” IEEE Trans. Comput., vol. C-37, pp. 274–282, Mar. 1988.
6. R. Gnanasekaran, “A fast serial-parallel binary multiplier,” IEEE Trans. Comput., vol. C-34, pp. 741–744, Aug. 1985.
7. J. P. Shen and F. J. Ferguson, “The design of easily testable VLSI array multipliers,” IEEE Trans. Comput., vol. C-33, pp. 554–560, June 1984.
8. T. G. Noll, D. S. Landsiedel, H. Klar, and G. Enders, “A pipelined 330-MHz multiplier,” IEEE J. Solid-State Circuits, vol. SC-21, pp. 411–416, June 1986.