Simulated SEU hardened scaled CMOS SRAM cell design using gated resistors

IEEE Transactions on Nuclear Science

Volumn 39, Issue 5, 1992, Pages 1532-1541

  Rockett, Leonard R ^a  

^a IBM   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

CMOS INTEGRATED CIRCUITS; RADIATION HARDENING; RESISTORS; SEMICONDUCTING SILICON;

GATED RESISTORS; SINGLE EVENT UPSETS;

RANDOM ACCESS STORAGE;

EID: 0026930097     PISSN: 00189499     EISSN: 15581578     Source Type: Journal    
DOI: 10.1109/23.173239     Document Type: Article

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