A Pipeline Processor for Mixed-Size FFT’s

IEEE Transactions on Signal Processing

Volumn 40, Issue 8, 1992, Pages 1892-1900

  Sayegh, Soheil I ^a  

^a Image Processing Department   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

FAST FOURIER TRANSFORMS;

PIPELINE ARCHITECTURE; TIMING DIAGRAMS;

DIGITAL SIGNAL PROCESSING;

EID: 0026907996     PISSN: 1053587X     EISSN: 19410476     Source Type: Journal    
DOI: 10.1109/78.149992     Document Type: Article

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