A 34-ns 16-Mb DRAM with Controllable Voltage Down-Converter

IEEE Journal of Solid-State Circuits

Volumn 27, Issue 7, 1992, Pages 1020-1027

  Hidaka, Hideto ^a   Arimoto, Kazutami ^a   Hirayama, Kazutoshi ^a   Hayashikoshi, Masanori ^a   Asakura, Mikio ^a   Tsukude, Masaki ^a   Oishi, Tsukasa ^a   Kawai, Shinji ^a   Suma, Katsuhiro ^a   Konishi, Yasuhiro ^a   Tanaka, Koji ^a   Wakamiya, Wataru ^a   Ohno, Yoshikazu ^a   Fujishima, Kazuyasu ^a  

^a MITSUBISHI ELECTRIC CORPORATION   (Japan)

Author keywords

[No Author keywords available]

Indexed keywords

AMPLIFIERS; DATA STORAGE, SEMICONDUCTOR; ELECTRONIC CIRCUITS; SEMICONDUCTOR MATERIALS--ION IMPLANTATION;

DRAM; HIGH-SPEED DRAM; SENSE AMPLIFIERS; VOLTAGE CONVERTERS; VOLTAGE DOWN-CONVERTERS;

DATA STORAGE, DIGITAL;

EID: 0026899541     PISSN: 00189200     EISSN: 1558173X     Source Type: Journal    
DOI: 10.1109/4.142597     Document Type: Article

References (12)

1. K. Arimoto et al., “A 60 ns 3.3 V only 16Mb DRAM with multipurpose register,” IEEE J. Solid-State Circuits, vol. 24, no. 10, pp. 1184–1190, 1989.
2. K. Arimoto et al., “A 34 ns 16Mb DRAM with controllable voltage down converter,'’ in Proc. European Solid-State Circuits Conf., 1991, pp. 21-24.
3. T. Yamada et al., “A 64Mb DRAM with meshed power line and distributed sense-amplifier driver,” in ISSCC Dig. Tech Papers, 1991, pp. 108-109.
4. Y. Oowaki et al., “A 33 ns 64Mb DRAM,” in ISSCC Dig. Tech Papers, 1991, pp. 114-115.
5. J. Okamura et al., “Decoded-source sense amplifier for high density DRAMs,” in Dig. Tech. Papers, 1989 Symp. VLSI Circuits, pp. 103104.
6. D. Chin et al., “An experimental 16Mb DRAM with reduced peak current noise,” in Dig. Tech. Papers, 1989 Symp. VLSI Circuits, pp. 113-114.
7. M. Horiguchi et al., “Dual-operating-voltage scheme for a single 5-V 16-Mbit DRAM,” IEEE J. Solid-State Circuits, vol. 23, pp. 1128–1132, Oct. 1988.
8. M. Horiguchi et al., “A tunable CMOS DRAM voltage limiter with stabilized feedback amplifier,” in Dig. Tech. Papers, 1990 Symp. VLSI Circuits, pp. 75-76.
9. M. Horiguchi et al., “Dual-regulator dual-decoding-trimmer DRAM voltage limiter for burn-in test,” in Dig. Tech. Papers, 1991 Symp. VLSI Circuits, pp. 127-128.
10. Y. Konishi et al., “A 38ns 4Mb DRAM with a battery backup (BBU) mode,” in ISSCC Dig. Tech Papers, 1990, pp. 230-231.
11. Y. Matsuda et al., “MeV-boron implanted buried barrier for soft error reduction in megabit DRAM,” in Extended Abstr. 19th Conf. Solid State Devices and Mater., 1987, pp. 23-26.
12. T. Kuroi, S. Komori, H. Miyatake, K. Tsukamoto, and Y. Akasaka, “Characteristics of junction leakage current of buried layer formed by high energy ion implantation,” in Extended Abstr. 22nd Conf. Solid State Devices and Mater., 1990, pp. 441-444.