The Effect of Silicon Gate Microstructure and Gate Oxide Process on Threshold Voltage Instabilities in p+-Gate p-Channel MOSFET’s with Fluorine Incorporation

IEEE Transactions on Electron Devices

Volumn 39, Issue 7, 1992, Pages 1687-1693

  Tseng, Hsing Huang ^a   Tobin, Philip J ^a   Baker, Frank K ^a   Pfiester, James R ^a   Evans, Keenan ^b   Fejes, L ^b  

^a MOTOROLA INC   (United States)

^b MOTOROLA INC   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

LOGIC DEVICES--GATES; SEMICONDUCTING SILICON--DOPING;

SILICON DEVICES;

SEMICONDUCTOR DEVICES, MOSFET;

EID: 0026897882     PISSN: 00189383     EISSN: 15579646     Source Type: Journal    
DOI: 10.1109/16.141235     Document Type: Article

References (12)

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