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Volumn 39, Issue 7, 1992, Pages 480-482

An RNS to Binary Converter in 2n + 1,2n, 2n - 1 Moduli Set

Author keywords

[No Author keywords available]

Indexed keywords

DIGITAL ARITHMETIC; MICROPROCESSOR CHIPS; MULTIPLYING CIRCUITS;

EID: 0026896902     PISSN: 10577130     EISSN: None     Source Type: Journal    
DOI: 10.1109/82.160172     Document Type: Article
Times cited : (48)

References (10)
  • 2
    • 0024070952 scopus 로고
    • An efficient residue to binary converter design
    • Sept.
    • K. M. Ibrahim and S. N. Saloum, “An efficient residue to binary converter design,” IEEE Trans. Circuits Syst., vol. 35, pp. 1156–1158, Sept. 1988.
    • (1988) IEEE Trans. Circuits Syst. , vol.35 , pp. 1156-1158
    • Ibrahim, K.M.1    Saloum, S.N.2
  • 3
    • 0024070868 scopus 로고
    • Residue to binary conversion for RNS arithmetic using only modular look-up tables
    • Sept.
    • A. P. Shenoy and R. Kumaresan, “Residue to binary conversion for RNS arithmetic using only modular look-up tables,” IEEE Trans. Circuits Syst., vol. 35, pp. 1158–1162, Sept. 1988.
    • (1988) IEEE Trans. Circuits Syst. , vol.35 , pp. 1158-1162
    • Shenoy, A.P.1    Kumaresan, R.2
  • 4
    • 0024104425 scopus 로고
    • A new efficient memoryless residue to binary converter
    • Nov.
    • S. Andraos and H. Ahmad, “A new efficient memoryless residue to binary converter,” IEEE Trans. Circuits Syst., vol. 35, pp. 1441–1444, Nov. 1988.
    • (1988) IEEE Trans. Circuits Syst. , vol.35 , pp. 1441-1444
    • Andraos, S.1    Ahmad, H.2
  • 5
    • 0024104042 scopus 로고
    • Efficient VLSI networks for converting an integer from binary sytstem to residue number system and vice verse
    • Nov.
    • R. M. Capocelli and R. Giancarlo, “Efficient VLSI networks for converting an integer from binary sytstem to residue number system and vice verse,” IEEE Trans. Circuits Syst., vol. 35, pp. 1425–1431, Nov. 1988.
    • (1988) IEEE Trans. Circuits Syst. , vol.35 , pp. 1425-1431
    • Capocelli, R.M.1    Giancarlo, R.2
  • 7
    • 0026407152 scopus 로고
    • Fast arithmetic based on residue number system architectures
    • Singapore, June
    • H. M. Yassine, “Fast arithmetic based on residue number system architectures,” IEEE Int. Symp. on Circuits and Systems, Singapore, June 1991, pp. 2947–2950.
    • (1991) IEEE Int. Symp. on Circuits and Systems , pp. 2947-2950
    • Yassine, H.M.1
  • 8
    • 0026384847 scopus 로고
    • Common VLSI architecture for a practically useful residue number system
    • Singapore, June
    • B. Arambepola, “Common VLSI architecture for a practically useful residue number system,” in IEEE Int. Symp. on Circuits and Systems, Singapore, June 1991, pp. 2951–2954.
    • (1991) IEEE Int. Symp. on Circuits and Systems , pp. 2951-2954
    • Arambepola, B.1


* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.