An Efficient Delay Test Generation System for Combinational Logic Circuits

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems

Volumn 11, Issue 7, 1992, Pages 926-938

  Park, Eun Sei ^a   Mercer, M Ray ^b  

^a Electronics and Telecommunications Research Institute (ETRI)   (South Korea)

^b UNIVERSITY OF TEXAS AT AUSTIN   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

MATHEMATICAL TECHNIQUES--ALGORITHMS;

TEST PATTERN GENERATION;

LOGIC CIRCUITS, COMBINATORIAL;

EID: 0026896741     PISSN: 02780070     EISSN: 19374151     Source Type: Journal    
DOI: 10.1109/43.144857     Document Type: Article

References (27)

1. E. P. Hsieh, R. A. Rasmussen, L. J. Vidunas, and W. T. Davis, “Delay test generation,” in Proc. 14th Design Automat. Conf., June 1977, pp. 486–491.
2. J. D. Lesser and J. J. Schedletsky, “An experimental delay test generation for LSI,” IEEE Trans. Comput., vol. C-29, pp. 235–248, Mar. 1980.
3. C. J. Lin and S. M. Reddy, “On delay fault testing in logic circuits,” IEEE Trans. Computer-Aided Design, vol. CAD-6, pp. 694–703, Sept. 1987.
4. G. L. Smith, “Model for delay faults based upon path,” in Proc. Int. Test Conf., Nov. 1985, pp. 342–349.
5. E. S. Park, M. R. Mercer, and T. W. Williams, “A statistical model for delay fault coverage,” IEEE Design and Test of Computers, pp. 45–55, Feb. 1989.
6. E. S. Park, M. R. Mercer, and T. W. Williams, “Statistical delay fault coverage and defect level for delay faults,” in Proc. Int. Test Conf., Sept. 1988, pp. 492–499.
7. A. K. Pramanick and S. M. Reddy, “On the computation of the ranges of detected delay fault sizes,” in Proc. Int. Conf Computer-Aided Design, Sept. 1989, pp. 126–129.
8. V. S. Iyengar, B. K. Rosen, and J. A. Waicukauski, “On computing the sizes of detected delay faults,” IEEE Trans. Computer-Aided Design, vol. 9, pp. 299–312, Mar. 1990.
9. J. Savir, and W. H. McAnney, “Random pattern testability of delay fault,” IEEE Trans. Comput., vol. 37, pp. 291–300, Mar. 1988.
10. J. A. Waicukauski, E. Lindbloom, B. Rosen, and V. Iyengar, “Transition fault simulation by parallel pattern single fault propagation,” in Proc. Int. Test. Conf., Sept. 1986, pp. 542–549.
11. P. Goel, “An implicit enumeration algorithm to generate tests for combinational logic circuits,” IEEE Trans. Comput., vol. C-30, pp. 215–222, Mar. 1981.
12. V. S. Iyengar, B. K. Rosen, and I. Spillinger, “Delay test generation 2—Algebra and algorithms,” in Proc. Int. Test Conf., Sept. 1988, pp. 867–874.
13. E. S. Park, “Delay testing: Figure of merit and test generation,” Ph.D. dissertation, Dept. Elec. Comput. Eng., Univ. of Texas, Austin, Aug. 1989.
14. F. F. Sellers, M. Y. Hsiao, and C. L. Beamson, “Analyzing errors with Boolean difference,” IEEE Trans. Comput., vol. C-17, pp. 676–683, July 1968.
15. E. S. Park and M. R. Mercer, “Robust and nonrobust tests for path delay faults in a combinational circuit,” in Proc. Int. Test Conf, Sept. 1987, pp. 1027–1034.
16. E. J. McCluskey, Logic Design Principles: With Emphasis on Testable Semicustom Circuits. Englewood Cliffs, NJ: Prentice-Hall, 1986, pp. 79–93.
17. C. T. Glover and M. R. Mercer, “A deterministic approach to adjacency testing for delay faults,” in Proc. 26th Design Automat. Conf., June 1989, pp. 351–356.
18. R. B. Hitchcock, G. L. Smith, and D. D. Cheng, “Timing analysis of computer hardwares,” IBM J. Res. Develop., vol. 26, no. 1, pp. 100-105, Jan. 1982.
19. T. Kirkland and M. R. Mercer, “A topological search algorithm for ATPG,” in Proc. 24th Design Automat. Conf, June 1987, pp. 502–508.
20. D. Harel, “A linear algorithm for finding dominators in flow graphs and related problems,” in Proc. 17th ACM Symp. Theory of Computing, 1985, pp. 185–194.
21. H. Fujiwara and T. Shimono, “On the acceleration of test generation algorithms,” IEEE Trans. Comput., vol. C-32, pp. 223–234, Dec. 1980.
22. M. H. Schulz and E. Auth, “Improved deterministic test pattern generation with applications to redundancy identification,” IEEE Trans. Computer-Aided Design, vol. 8, pp. 811–816, July 1989.
23. F. Brglez and H. Fujiwara, “Neutral netlist of ten combinational benchmark circuits and a target translator in FORTRAN” (Special session on ATPG and fault simulation), in Proc. IEEE Int. Symp. Circuits Syst. June 1985.
24. A. K. Pramanick and S. M. Reddy, “On the detection of delay faults,” in Proc. Int. Test Conf, Sept. 1988, pp. 845–856.
25. D. Brand and V. S. Iyengar, “Timing analysis using functional analysis,” IEEE Trans. Comput., vol. 37, pp. 1309–1314, Oct. 1988.
26. P. G. McGeer and R. K. Brayton, “Efficient algorithms for computing the longest viable path in a combinational network,” in Proc. 26th Design Automat. Conf., July 1989, pp. 561–567.
27. F. Maamari and J. Rajski, “A reconvergent fanout analysis for efficient exact fault simulation of combinational circuits,” in Proc. 18th Fault Tolerant Computing Symp., June 1988, pp. 122–127.