Modular Multiplication Hardware Algorithms with a Redundant Representation and Their Application to RSA Cryptosystem

IEEE Transactions on Computers

Volumn 41, Issue 7, 1992, Pages 887-891

  Takagi, Naofumi ^a   Yajima, Shuzo ^a  

^a KYOTO UNIVERSITY   (Japan)

Author keywords

Computer arithmetic, cryptosystem, hardware algorithm; modular multiplication; redundant representation; VLSI

Indexed keywords

COMPUTERS, DIGITAL--MULTIPLYING CIRCUITS; CRYPTOGRAPHY;

PUBLIC-KEY CRYPTOSYSTEMS;

MATHEMATICAL TECHNIQUES;

EID: 0026888035     PISSN: 00189340     EISSN: None     Source Type: Journal    
DOI: 10.1109/12.256444     Document Type: Article

References (9)

1. R. L. Rivest, A. Shamir, and L. Adleman, “A method for obtaining digital signatures and public-key cryptosystems,” Commun. ACM, vol. 21, no. 2, pp. 120–126, Feb. 1978.
2. E. F. Brickell, “A survey of hardware implementations of RSA,” Lecture Notes in Computer Science, vol. 435, G. Brassard, Ed., Advances in Cryptology — CRYPTO’89 Proc. New York: Springer-Verlag, 1990, pp. 368–370.
3. E. F. Brickell, “A fast modular multiplication algorithm with application to two key cryptography,” in Advances in Cryptology, Proc. CRYPTO 82, D. Chaum et al., Eds. New York: Plenum, 1983, pp. 51–60.
4. H. Morita, “A fast modular-multiplication algorithm based on a higher radix,” in Lecture Notes in Computer Science, vol. 435, G. Brassard Ed., Advances in Cryptology — CRYPTO’89 Proc. New York: Springer-Verlag, 1990, pp. 387–399.
5. N. Takagi, Y. Okabe, H. Yasuura, and S. Yajima, “Modulo m addition using redundant representation and its application to residue-number/binary conversion,” Rep. Tech. Group on Computation, IECEJ, COMP86-14, June 1986 (in Japanese).
6. N. Takagi, “Studies on hardware algorithms for arithmetic operations with a redundant binary representation,” Doctoral dissertation, Dep. Inform. Sci., Kyoto Univ., Aug. 1987.
7. A. Avizienis, “Signed-digit number representations for fast parallel arithmetic,” IRE Trans. Electron. Comput., vol. EC-10, no. 3, pp. 389–400, Sept. 1961.
8. N. Takagi, H. Yasuura, and S. Yajima, “High-speed VLSI multiplication algorithm with a redundant binary addition tree,” IEEE Trans. Comput., vol. C-34, no. 9, pp. 789–796, Sept. 1985.
9. H. Yasuura, N. Takagi, and S. Yajima, “Redundant coding for local computability,” Perspectives in computing, vol. 15, D. S. Johnson et al., Eds., Discrete algorithms and complexity: Proceedings of Japan-US Joint Seminar 1986. New York: Academic, 1987, pp. 145–159.