A Voltage Down Converter with Submicroampere Standby Current for Low-Power Static RAM’s

IEEE Journal of Solid-State Circuits

Volumn 27, Issue 6, 1992, Pages 920-926

  Ishibashi, Koichiro ^a   Sasaki, Katsuro ^a   Toyoshima, Hiroshi ^a  

^a HITACHI LTD   (Japan)

Author keywords

[No Author keywords available]

Indexed keywords

ELECTRONIC CIRCUITS; SEMICONDUCTOR DEVICES, MOSFET--APPLICATIONS;

LOW-POWER STATIC RAM'S; STANDBY/OPERATION MODES; SUBMICROAMPERE STANDBY CURRENT; VOLTAGE DOWN CONVERTER (VDC); VOLTAGE-FOLLOWER CIRCUITS;

DATA STORAGE, DIGITAL;

EID: 0026880611     PISSN: 00189200     EISSN: 1558173X     Source Type: Journal    
DOI: 10.1109/4.135336     Document Type: Article

References (10)

1. S. Hayakawa et. al., “A 1 μA retention 4 Mb SRAM with a thin-film-transistor load cell,” in ISSCC Dig. Tech. Papers, Feb. 1990, pp. 128–129.
2. S. Aizaki et. al., “A 15 ns 4 Mb CMOS SRAM,” in ISSCC Dig. Tech. Papers, Feb. 1990, pp. 126–127.
3. A. L. Roberts et. al., “A 256K SRAM with on-chip power supply conversion,” in ISSCC Dig. Tech. Papers, Feb. 1987, pp. 252–253.
4. S. Hayakawa et. al., “A process-insensitivity voltage down converter suitable for half-micron SRAM’s,” in Symp. VLSI Circ., Dig. Tech. Papers, May 1988, pp. 53–54.
5. K. Sasaki et. al., “A 9-ns 1-Mbit CMOS SRAM,” IEEE J. Solid-State Circuits, vol. 24, pp. 1219–1225, Oct. 1989.
6. S. M. Sze, Physics of Semiconductor Devices, 2nd ed. New York: Wiley, 1981, p. 474.
7. T. Douseki et. al., “Fast-access BiCMOS SRAM architecture with a VSS generator,” in Symp. VLSI Circ., Dig. Tech. Papers, May 1990, pp. 45–46.
8. R. A. Blaushild et. al., “An NMOS voltage reference,” in ISSCC Dig. Tech. Papers, Feb. 1978, pp. 50–51.
9. K. Sasaki et. al., “A 23 ns 4 Mb CMOS SRAM with 0.5 μA standby current,” in ISSCC Dig. Tech. Papers, Feb. 1990, pp. 130–131.
10. P. R. Gray and R. G. Mayer, Analysis and Design of Analog Integrated Circuits, 2nd ed. New York: Wiley, 1984, p. 543.