Design and Optimization of Buffer Chains and Logic Circuits in a BiCMOS Environment

IEEE Journal of Solid-State Circuits

Volumn 27, Issue 5, 1992, Pages 792-801

  Elrabaa, Muhammad S ^a   Elmasry, Mohamed I ^a  

^a UNIVERSITY OF WATERLOO   (Canada)

Author keywords

[No Author keywords available]

Indexed keywords

ELECTRONIC CIRCUITS, BUFFER; INTEGRATED CIRCUITS, CMOS; INTEGRATED CIRCUITS, DIGITAL; LOGIC DEVICES - GATES; OPTIMIZATION;

BICMOS BUFFER CHAINS; BICMOS COMPLEX LOGIC GATES; CMOS/BICMOS BUFFERS; CURRENT MODE LOGIC; MULTILEVEL LOGIC GATES;

LOGIC DESIGN;

EID: 0026866287     PISSN: 00189200     EISSN: 1558173X     Source Type: Journal    
DOI: 10.1109/4.133170     Document Type: Article

References (13)

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