Parallel contention resolution control for input queueing ATM switches

Electronics Letters

Volumn 28, Issue 9, 1992, Pages 838-839

  Obara, H ^a   Hamazumi, Y ^a  

^a NTT CORPORATION   (Japan)

Author keywords

Digital communication systems; Parallel processing

Indexed keywords

BUSINESS MACHINES - AUTOMATED TELLER MACHINES; COMPUTER ARCHITECTURE - OPTIMIZATION; COMPUTER PROGRAMMING - ALGORITHMS; COMPUTER SYSTEMS, DIGITAL - PIPELINE PROCESSING; PROBABILITY - QUEUEING THEORY;

INPUT QUEUEING ATM SWITCHES; PARALLEL CONTENTION CONTROL;

COMPUTER SYSTEMS, DIGITAL;

EID: 0026851180     PISSN: 00135194     EISSN: None     Source Type: Journal    
DOI: 10.1049/el:19920530     Document Type: Article

References (6)

1. OBARA, H., and YASUSHI, T.: ‘High speed transport processor for broadband burst transport system’. Proc. IEEE Int. Conf. on Communications, Philadelphia, 1988, pp. 922-927
2. OBARA, H., SASAGAWA, M., and TOKIZAWA, I.: ‘An ATM crossconnect system for broadband transport networks based on virtual path concept’. Proc. of the IEEE Int. Conf. on Communications, Atlanta, 1990, pp. 839-843
3. HUI, J. Y., and ARTHURS, E.: ‘A broadband packet switch for integrated transport’, IEEE J. Sel. Areas Commun., 1987, SAC-5, (8), pp. 1264-1273
4. UEMATSU, H., MATSUNAGA, H., and OBARA, H.: ‘A cell based crossconnect switch for ATM broadband networks’. Proc. of Singapore Int. Conf. on Networks, Singapore, 1989, pp. 371-376
5. OBARA, H.: ‘Optimum architecture for input queueing ATM switches’, Electron. Lett., 1991, 27, (7), pp. 555-556
6. OBARA, H., OKAMOTO, S., and HAMAZUMI, Y.: ‘Input and output queueing ATM switch architecture with spatial and temporal slot reservation control’, Electron. Lett., 1992, 28, (1), pp. 22-24