메뉴 건너뛰기




Volumn 39, Issue 4, 1992, Pages 921-931

Parametric Study of Latchup Immunity of Deep Trench-Isolated, Bulk, Nonepitaxial CMOS

Author keywords

[No Author keywords available]

Indexed keywords

MATHEMATICAL MODELS; SUBSTRATES;

EID: 0026851062     PISSN: 00189383     EISSN: 15579646     Source Type: Journal    
DOI: 10.1109/16.127484     Document Type: Article
Times cited : (7)

References (12)
  • 1
    • 0021444403 scopus 로고
    • A CMOS structure with a high latchup holding voltage
    • G. J. Hu and R. H. Bruce, “A CMOS structure with a high latchup holding voltage,” IEEE Electron Device Lett., vol. EDL-5, p. 211, 1984.
    • (1984) IEEE Electron Device Lett , vol.EDL-5 , pp. 211
    • Hu, G.J.1    Bruce, R.H.2
  • 3
    • 0020293036 scopus 로고
    • Deep trench isolated CMOS devices
    • San Francisco, CA, Dec. abstr. 9.6
    • R. D. Rung, H. Momose, and Y. Nagakubo, “Deep trench isolated CMOS devices,” in IEDM Tech. Dig. (San Francisco, CA, Dec. 1982), abstr. 9.6, pp. 237–240.
    • (1982) IEDM Tech. Dig , pp. 237-240
    • Rung, R.D.1    Momose, H.2    Nagakubo, Y.3
  • 5
    • 84941429888 scopus 로고
    • Advanced techniques for CMOS performance enhancement and latchup control
    • Ph.D. dissertation, Dept, of E. E. and C. S., Univ. of California at Berkeley
    • H. P. Zappe, “Advanced techniques for CMOS performance enhancement and latchup control,” Ph.D. dissertation, Dept, of E. E. and C. S., Univ. of California at Berkeley, 1989.
    • (1989)
    • Zappe, H.P.1
  • 6
    • 0021640278 scopus 로고
    • Trench isolation prospects for application in CMOS VLSI
    • abstr. 26.1
    • R. D. Rung, “Trench isolation prospects for application in CMOS VLSI,” in IEDM Tech. Dig., 1984, abstr. 26.1, pp. 574–577.
    • (1984) IEDM Tech. Dig , pp. 574-577
    • Rung, R.D.1
  • 7
    • 0023331957 scopus 로고
    • An analytic model of holding voltage for latchup in epitaxial CMOS
    • J. A. Seitchik, A. Chatterjee, and P. Yang, “An analytic model of holding voltage for latchup in epitaxial CMOS,” IEEE Electron Device Lett., vol. EDL-8, pp. 157–159, 1987.
    • (1987) IEEE Electron Device Lett , vol.EDL-8 , pp. 157-159
    • Seitchik, J.A.1    Chatterjee, A.2    Yang, P.3
  • 8
    • 0025577837 scopus 로고
    • Design issues for achieving latchup-free, deep trench-isolated, bulk, non-epitaxial, submicron CMOS
    • (San Francisco, CA)
    • S. Bhattacharya, S. Banerjee, J. Lee, A. Tasch, and A. Chatterjee, “Design issues for achieving latchup-free, deep trench-isolated, bulk, non-epitaxial, submicron CMOS,” in IEDM Tech. Dig., 1990 (San Francisco, CA), pp. 185–188.
    • (1990) IEDM Tech. Dig , pp. 185-188
    • Bhattacharya, S.1    Banerjee, S.2    Lee, J.3    Tasch, A.4    Chatterjee, A.5
  • 9
    • 0003672607 scopus 로고
    • PISCES-II: Poisson and continuity equation solver
    • TMA PISCES was used in this work
    • M. R. Pinto, C. S. Rafferty, and R. W. Dutton, “PISCES-II: Poisson and continuity equation solver,” Stanford Electronics Labs. Rep., 1984. TMA PISCES was used in this work.
    • (1984) Stanford Electronics Labs. Rep
    • Pinto, M.R.1    Rafferty, C.S.2    Dutton, R.W.3
  • 10
    • 30244572023 scopus 로고
    • Forward characteristics of thyristors in the fired state
    • A. Herlet and K. Raithel, “Forward characteristics of thyristors in the fired state,” Solid-State Electron., vol. 9, p. 1089, 1966.
    • (1966) Solid-State Electron , vol.9 , pp. 1089
    • Herlet, A.1    Raithel, K.2
  • 12
    • 0014318424 scopus 로고
    • The forward characteristic of silicon power rectifiers at high current densities
    • A. Herlet, “The forward characteristic of silicon power rectifiers at high current densities,” Solid-State Electron., vol. 11, p. 717, 1968.
    • (1968) Solid-State Electron , vol.11 , pp. 717
    • Herlet, A.1


* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.