Synthesis of Robust Delay-Fault-Testable Circuits: Practice

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems

Volumn 11, Issue 3, 1992, Pages 277-300

  Devadas, Srinivas ^a   Keutzer, Kurt ^b  

^a MASSACHUSETTS INSTITUTE OF TECHNOLOGY   (United States)

^b SYNOPSYS INC   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

COMPUTER METATHEORY - BOOLEAN FUNCTIONS; CRYPTOGRAPHY; INTEGRATED CIRCUITS, VLSI - TESTING; LOGIC DESIGN; SPEECH - RECOGNITION;

ALGEBRAIC FACTORIZATION; BOOLEAN FACTORIZATION; DATA ENCRYPTION CHIP; DELAY-FAULT-TESTABLE CIRCUITS; GATE-DELAY-FAULT TESTABILITY; HEURISTIC COVERING ALGORITHM;

LOGIC CIRCUITS;

EID: 0026839944     PISSN: 02780070     EISSN: 19374151     Source Type: Journal    
DOI: 10.1109/43.124416     Document Type: Article

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