Analysis and Design of Latch-Controlled Synchronous Digital Circuits

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems

Volumn 11, Issue 3, 1992, Pages 322-333

  Sakallah, Karem A ^a   Mudge, Trevor N ^a   Olukotun, Oyekunle A ^b  

^a UNIVERSITY OF MICHIGAN   (United States)

^b STANFORD UNIVERSITY   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

ELECTRONIC CIRCUITS, TIMING; LOGIC DESIGN; MATHEMATICAL PROGRAMMING, LINEAR;

CLOCKING METHODOLOGY; LATCH CONSTRAINTS; LATCH-CONTROLLED DIGITAL CIRCUITS; SYNCHRONOUS DIGITAL CIRCUITS;

INTEGRATED CIRCUITS, DIGITAL;

EID: 0026835178     PISSN: 02780070     EISSN: 19374151     Source Type: Journal    
DOI: 10.1109/43.124419     Document Type: Article

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