Simple binary random number generator

Electronics Letters

Volumn 28, Issue 7, 1992, Pages 617-618

  Bellido, M J ^a   Acosta, A J ^a   Valencia, M ^a   Barriga, A ^a   Huertas, J L ^a  

^a Centro Informatico Cientifico de Andalucia   (Spain)

Author keywords

Integrated circuits; Latches

Indexed keywords

ELECTRONIC CIRCUITS, SWITCHING; INTEGRATED CIRCUITS, CMOS;

BINARY RANDOM NUMBERS; CMOS LATCHES; LATCHES; RANDOM NUMBER GENERATORS;

MATHEMATICAL STATISTICS;

EID: 0026832107     PISSN: 00135194     EISSN: None     Source Type: Journal    
DOI: 10.1049/el:19920389     Document Type: Article

References (5)

1. HORTENSIUS, P. D., MCLEOD, R. D., and CARD, H. C.: ‘Parallel random number generation for VLSI systems using cellular automata’, IEEE Trans., 1989, C-38, (10), pp. 1466-1472
2. HORTENSIUS, P. D., MCLEOD, R. D., PRIES, W., MILLER, M., and CARD, H. C.: ‘Cellular automata-based pseudorandom number generators for built-in self-test’, IEEE Trans., 1989, CAD-8, (8), pp. 842-849
3. SALIDES, P., YORK, T. A., and THANAILAKIS, A.: ‘Pseudorandom number generators for VLSI systems based on linear cellular automata’, IEE Proc. E, 1991,138, (4), pp. 241-249
4. RODRIGUEZ-VAQUEZ, A., DELGADO, M., ESPEJO, S., and HUERTAS, J. L.: ‘Switched-capacitor broadband noise generator for CMOS VLSI’, Electron. Lett., 1991, 27, (21), pp. 1913-1915
5. ROSEMBERG, F., and CHANEY, T. J.: ‘Flip-flop resolving time test circuit’, IEEE J. Solid-State Circuits, 1982, SC-17, (4), p. 731-738