A High-Speed CMOS Comparator with 8-b Resolution

IEEE Journal of Solid-State Circuits

Volumn 27, Issue 2, 1992, Pages 208-211

  Yin, G M ^a   Sansen, W ^a   Eynde, F Op’t ^b  

^a UNIVERSITY OF LEUVEN   (Belgium)

^b LUCENT TECHNOLOGIES   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

ELECTRONIC CIRCUITS, FLIP FLOP--OPTIMIZATION; OPTIMIZATION--APPLICATIONS; SEMICONDUCTING SILICON--APPLICATIONS; SEMICONDUCTOR DEVICES, MOS--APPLICATIONS;

DIFFERENTIAL INPUT STAGE; DOUBLE-POLY DOUBLE-METAL N-WELL PROCESS; HIGH-SPEED CMOS COMPARATOR; REGENERATIVE FLIP FLOPS;

ELECTRONIC CIRCUITS, COMPARATOR;

EID: 0026821719     PISSN: 00189200     EISSN: 1558173X     Source Type: Journal    
DOI: 10.1109/4.127344     Document Type: Article

References (7)

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3. B. J. McCarroll, C. G. Sodini, and H-S. Lee, “A high speed CMOS comparator for use in an ADC,” IEEE J. Solid-State Circuits, vol. 23, pp. 159–165, Feb. 1988.
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7. F. Op’t Eyend, G. M. Yin, and W. Sansen, “A CMOS fourth-order 14b 500k-sample/s sigma-delta ADC converter,” in ISSCC Dig. Tech. Papers, Feb. 1991, pp. 62–63.