ESD Failure Modes: Characteristics, Mechanisms and Process Influences

IEEE Transactions on Electron Devices

Volumn 39, Issue 2, 1992, Pages 430-436

  Schofield, Paul ^d   Hannemann, Marcel ^c  

^a TEXAS INSTRUMENTS   (United States)

^b Actel Corp   (United States)

^c PHILIPS RESEARCH LABORATORIES   (Netherlands)

^d The Isle of Man Government Laboratory   (United Kingdom)

Author keywords

[No Author keywords available]

Indexed keywords

ELECTRIC DISCHARGES; ELECTROSTATICS;

BARRIER METALLIZATION; CMOS PROCESSES; ELECTROSTATIC DISCHARGES; LIGHTLY DOPED DRAINS; SILICIDES; THIN GATE OXIDES;

INTEGRATED CIRCUITS, CMOS;

EID: 0026817821     PISSN: 00189383     EISSN: 15579646     Source Type: Journal    
DOI: 10.1109/16.121703     Document Type: Article

References (8)

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2. A. Amerasekera, L. van Roozendaal, J. Bruines, and F. Kuper, “Characterization and modeling of second breakdown in NMOST’s for the extraction of ESD-related process and design parameters,” IEEE Trans. Electron Devices, vol. 38, pp. 2161–2168, Sept. 1991.
3. R. A. McPhee, C. Duvvury, R. Rountree, and H. Domingos, “Thick oxide performance under process variations,” in Proc. 8th EOS/ESD Symp., 1986, pp. 173–181.
4. K-L. Chen, “Effect of interconnect process and snapback voltage on the ESD failure threshold of NMOS transistor,” in Proc. 10th EOS/ ESD Symp., 1988, pp. 212–219.
5. R. N. Roundtree and C. L. Hutchins, “NMOS protection circuitry,” IEEE Trans. Electron Devices, vol. ED-32, pp. 910–917, 1985.
6. G. Krieger, “Thermal response of integrated circuit input devices to an electrostatic energy pulse,” IEEE Trans. Electron Devices., vol. ED-34, pp. 877–882, 1987.
7. P-H. Chang, R. Hawkins, T. D. Bonifield, and L. A. Melton, “Aluminum spiking in contact windows in Al/Ti-W/Si,” Appl. Phys. Lett., vol. 52, pp. 272–274, 1988.
8. D. G. Pierce, “Electro-thermomigration as an electrical overstress failure mechanism,” in Proc. 8th EOS/ESD Symp., 1986, pp. 67–76.