Analytical Transient Response of CMOS Inverters

IEEE Transactions on Circuits and Systems I: Fundamental Theory and Applications

Volumn 39, Issue 1, 1992, Pages 42-45

  Kayssi, Ayman I ^a   Sakallah, Karem A ^a   Burks, Timothy M ^a  

^a UNIVERSITY OF MICHIGAN   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

COMPUTER SIMULATION; ELECTRIC NETWORKS, NONLINEAR; ELECTRIC WAVEFORMS; INTEGRATED CIRCUITS, CMOS; MATHEMATICAL TECHNIQUES - DIFFERENTIAL EQUATIONS;

CMOS INVERTER TRANSIENTS; INVERTER PROPAGATION DELAY; SPICE CIRCUIT SIMULATOR;

ELECTRIC INVERTERS;

EID: 0026759921     PISSN: 10577122     EISSN: None     Source Type: Journal    
DOI: 10.1109/81.109241     Document Type: Article

References (8)

1. J. R. Burns, “Switching response of complementary-symmetry MOS transistor logic circuits,” RCA Review, vol. 25, pp. 627–661, 1964.
2. N. Hedenstierna and K. O. Jeppson, “CMOS circuit speed and buffer optimization,” IEEE Trans. Computer-Aided Design, pp. 270–281, Mar. 1987.
3. H. Shichman and D. A. Hodges, “Modeling and simulation of insulated-gate field-effect transistor switching circuits,” IEEE J. Solid-State Circuits, pp. 285–289, Sept. 1968.
4. E. Kamke, Differentialgleichungen, Lösungsmethoden und Lösungen. I. Gewöhnliche Differentialgleichungen, Chelsea, 1948.
5. J. K. Ousterhout, “Switch-level delay models for digital MOS VLSI,” in Proc. 21st ACM/IEEE Design Automation Conf., pp. 542–548, 1984.
6. Meta-Software Staff, HSPICE User's Manual, Meta-Software, 1991.
7. T. Sakurai and A. R. Newton, “Alpha-power law MOSFET model and its applications to CMOS inverter delay and other formulas,” IEEE J. Solid-State Circuits, pp. 584–594, Apr. 1990.
8. R. Putatunda, “Autodelay: A second generation automatic delay calculation program for LSI/VLSI chips,” in Proc. IEEE Int. Conf. Computer-Aided Design, pp. 188–189, 1984.