An Analog Neural Computer with Modular Architecture for Real-Time Dynamic Computations

IEEE Journal of Solid-State Circuits

Volumn 27, Issue 1, 1992, Pages 82-92

  der Spiegel, Jan Van ^a   Mueller, Paul ^a   Blackman, David ^a   Donham, Christopher ^a   Etienne Cummings, Ralph ^a   Chance, Peter ^b   Kinget, Peter ^c  

^a UNIVERSITY OF PENNSYLVANIA   (United States)

^b Corticon Inc ^*  (United States)

^c UNIVERSITY OF LEUVEN   (Belgium)

Author keywords

[No Author keywords available]

Indexed keywords

COMPUTER ARCHITECTURE; COMPUTERS, ANALOG; INTEGRATED CIRCUITS, CMOS;

ANALOG NEURAL COMPUTER; CROSSPOINT SWITCH CHIP; MODULAR ARCHITECTURE; NEURON MODULE; SPATIO-TEMPORAL PROCESSING; SYNAPSE MODULE;

NEURAL NETWORKS;

EID: 0026679533     PISSN: 00189200     EISSN: 1558173X     Source Type: Journal    
DOI: 10.1109/4.109559     Document Type: Article

References (30)

1. T. Sejnowski, C. Koch, and P. S. Churchland, “Computational neuroscience,” Science, vol. 241, pp. 1299–1306, 1988.
2. S. Grossberg, Studies of Mind and Brain, vol. 70, R. Cohen and M. Wartofskey, Eds. Boston, MA: D. Reidel, 1982.
3. J. Hopfield, “Neurons with graded response have collective computational properties like those of two-state neurons,” Proc. Nat. Acad. Sci., vol. 81, pp. 3088–3092, 1984.
4. D. E. Rumelhart and J. L. McClelland, Eds., Parallel Distributed Processing: Explorations in the Microstructures of Cognition, vols. 1, 2. Cambridge, MA: MIT Press, 1986.
5. T. Kohonen, “Correlation matrix memories,” IEEE Trans. Comput., vol. C-21, pp. 353–359, 1972.
6. P. Mueller, T. Martin, and F. Putzrath, “General principles of operations in neuron nets with application to acoustical pattern recognition,” Biological Prototypes and Synthetic Systems, vol. 1. New York: Plenum, 1962, pp. 192–212.
7. B. Widrow and M. E. Hoff, “Adaptive switching circuits,” in 1960 IRE WESCON, Conv. Rec. (New York), vol. IRE, 1960, pp. 96–104.
8. L. E. Atlas and Y. Suzuki, “Digital systems for artificial neural networks,” IEEE Circuits Devices, pp. 20–24, 1989.
9. M. Ysunaga et a!., “Design, fabrication and evaluation of a 5-inch wafer scale neural network LSI composed of 576 digital neurons,” in Proc. IJCNN Int. Joint Conf. Neural Networks, vol. II, 1990, pp. 527–535.
10. R. Hecht-Nielsen, “Neurocomputing: Picking the human brain,” IEEE Spectrum, pp. 36–41, in 1988.
11. H. P. Graf and L. Jackel, “Analog electronic neural network circuit,” IEEE Circuits Devices Mag., pp. 44–49, July 1989.
12. H. Graf and D. Henderson, “A reconfigurable CMOS neural network,” in ISSCC Dig. Tech. Papers, 1990, pp. 144–145.
13. B. Boser and E. Sackinger, “An analog neural network processor with programmable network topology,” in ISSCC Dig. Tech. Papers, 1991, pp. 184–185.
14. S. Satyanarayana, Y. Tsividis, and H. P. Graf, “A reconfigurable analog VLSI neural network chip,” in Advances in Neural Information Processing Systems 2, D. Touretzky, Ed. San Mateo, CA: Morgan Kaufmann, 1990, pp. 758–768.
15. J. Raffel, J. Mann, R. Berger, A. Soares, and S. Gilbert, “Electronic implementation of neuromorphic systems,” in Proc. IEEE Custom Int. Circuits Conf., 1988, pp. 10.1.1-10.1.7.
16. J. Alspector and R. B. Allen, “A neuromorphic VLSI learning system,” in Advanced Research VLSI, Proc. 1987 Stanford Conf.
17. J. White et al., “Parallel architecture of 2D Gaussian convolution of images,” Neural Networks, vol. 1, p. 415, 1988.
18. M. Holler, S. Tam, H. Castro, and R. Benson, “An electrically trainable artificial neural network etann with 10240 floating gate synapses,” in IJCNN Int. Joint Conf. Neural Networks, vol. 2, 1989, pp. 191–196.
19. A. Moopenn, T. Duong, and A. Thakoor, “Digital-analog hybrid synapse chips for electric neural networks,” in Advances in Neural Information Processing Systems, 2, D. Touretzky, Ed. San Mateo, CA: Morgan Kaufmann, 1990, pp. 769–776.
20. C. Mead, Analog VLSI and Neural Systems. Reading, MA: Addison-Wesley, 1989.
21. P. Mueller et al., “Design and fabrication of VLSI components for a general purpose analog neural computer,” in IEEE Workshop Analog VLSI Implementation of Neural Systems, Circuits Syst. Conf. (Portland), C. Mead and M. Ismail, Eds. Boston: Kluwer, 1989.
22. N. Farhat, “Optoelectronic neural networks and learning machines,” IEEE Circuits Devices, pp. 32–41, 1989.
23. K. Kyuma, “Optical architectures for neuron circuits,” in Proc. 1991 IEEE Int. Symp. Circuits Syst. (ISCAS9I), vol. 3, pp. 1384–1387.
24. P. Mueller and J. Lazzaro, “A machine for neural computation of acoustical patterns with application to real speech recognition,” in AIP Conf. Proc., vol. 151, 1986, pp. 321–326.
25. K. Bult and H. Wallinga, “A CMOS four-quadrant analog multiplier,” IEEEJ. Solid-State Circuits, vol. SC-21, no. 3, pp. 430–435, June 1986.
26. M. Steyaert, P. Kinget, W. Sansen, and J. Van der Spiegel, “Full integration of extremely large time constants in CMOS,” Electron. Lett., vol. 27, no. 10, pp. 790–791, 1991.
27. P. Mueller, et al., “Design and performance of a prototype general purpose analog neural computer,” in Proc. Int. Joint Conf Neural Networks (IJCNN), vol. I, 1991, pp. 463–468.
28. J. Van der Spiegel et al., “A multichip analog neural networks,” in Proc. Int. Symp. VLSI Tech. Syst. Applications, VLSITSA, 1991, pp. 64–68.
29. P. Mueller et al., “Design and performance of a prototype analog neural computer,” in Proc. 2nd DOD Workshop Neural Networks (Huntsville, AL), Sept. 1991.
30. P. Mueller, “Computation of pattern primitives in a neural network of acoustical pattern recognition,” in Proc. Int. Joint Conf. Neural Networks (IJCNN), vol. I, 1990, pp. 149–151.