A Third-Order Multistage Sigma-Delta Modulator with Reduced Sensitivity to Nonidealities

IEEE Journal of Solid-State Circuits

Volumn 26, Issue 12, 1991, Pages 1764-1774

  Fujii, Toshiaki ^b   Baertsch, Richard D ^a   Garverick, Steven L ^a   McGrath, Donald T ^a   Krisciunas, Joseph E ^a  

^a GE GLOBAL RESEARCH   (United States)

^b SEIKO INSTRUMENTS INC   (Japan)

Author keywords

[No Author keywords available]

Indexed keywords

ELECTRONIC CIRCUITS, INTEGRATING--APPLICATIONS; NOISE, SPURIOUS SIGNAL--SIGNAL TO NOISE RATIO; SEMICONDUCTOR DEVICES, MOS--APPLICATIONS;

CMOS DOUBLE-POLY TECHNOLOGY; NONIDEALITIES SENSITIVITY; RATIOLESS INPUT CIRCUITRY; SIGNAL TO DISTORTION RATIO; THIRD-ORDER MULTISTAGE SIGMA-DELTA MODULATOR;

MODULATORS;

EID: 0026407131     PISSN: 00189200     EISSN: 1558173X     Source Type: Journal    
DOI: 10.1109/4.104167     Document Type: Article

References (20)

1. W. L. Lee and C. G. Sodini, “A topology for higher order interpolative coders,” in Proc. IEEE Int. Symp. Circuits Syst., May 1987, pp. 459–462.
2. D. R. Welland et al., “A 16-bit delta-sigma A/D converter for digital audio,” J. Audio Eng. Soc., vol. 37, no. 6, June 1989.
3. P. Ferguson et al., “An 18 b 20 kHz dual sigma-delta A/D converter,” in ISSCC Dig. Tech. Papers, Feb. 1991, pp. 68–69.
4. T. Hayashi et al., “A multistage delta-sigma modulator, without double integrator loop,” in ISSCC Dig. Tech. Papers, Feb. 1986, pp. 182–183.
5. Y. Matsuya et al., “A 16-bit oversampling A-D conversion technology using triple integration noise shaping,” IEEE J. Solid-State Circuits, vol. SC-22, no. 6, pp. 921–929, Dec. 1987.
6. M. Rebeschini et al., “A 16-bit 160-kHz CMOS A/D converter using sigma-delta modulation,” IEEE J. Solid-State Circuits, vol. 25, pp. 431–440, Apr. 1990.
7. L. Longo and M. A. Copeland, “A 13-bit ISDN-band ADC using two-stage third order noise shaping,” in Proc. 1988 Custom Integrated Circuit Conf, June 1988, pp. 21.2.1-4.
8. D. B. Ribner, “A comparison of modulator networks for high-order oversampled sigma delta analog-to-digital converters,” IEEE Trans. Circuits Syst., vol. 38, no. 2, pp. 145–159, Feb. 1991.
9. D. B. Ribner et al., “A 16b third-order sigma delta modulator with reduced sensitivity to nonidealities,” in ISSCC Dig. Tech. Papers (San Francisco, CA), Feb. 1991, pp. 66–67.
10. B. P. Brandt and B. A. Wooley, “A CMOS oversampling A/D converter with 12b resolution at conversion rates above 1 MHz,” in ISSCC Dig. Tech. Papers (San Francisco, CA), Feb. 1991, pp. 64–65.
11. L. A. Williams, III, and B. A. Wooley, “Third-order cascaded sigma-delta modulators,” IEEE Trans. Circuits Syst., vol. 38, pp. 489–498, May 1991.
12. K.C.-H. Chao, S. Nadeem, W. L. Lee, and C. G. Sodini, “A higher order topology for interpolative modulators for oversampling A/D converters,” IEEE Trans. Circuits Syst., vol. 37, pp. 309–318, Mar. 1990.
13. R. Adams, P. Ferguson, and A. Ganesan, “Design of single-bit noise-shaping loops with high-order loop filters,” in Proc. 89th Conv. Audio Eng. Soc., Sept. 1990.
14. B. Boser and B. Wooley, “Simulating and testing oversampled analog-to-digital converters,” IEEE Trans. Computer-Aided Design, vol. 7, June 1988.
15. C. M. Wolff and L. R. Carley, “Simulation of delta-sigma modulators using behavioral models,” in Proc. 1990 IEEE Int. Circuits Syst. (New Orleans), May 1990, pp. 376–379.
16. F. J. Harris, “On the use of windows for harmonic analysis with the discrete Fourier transform,” Proc. IEEE, vol. 66, pp. 51–83, Jan. 1978.
17. K. C. Hsieh, P. R. Gray, D. Senderowicz, and D. G. Messerschmitt, “A low-noise chopper-stabilized differential switched-capacitor filtering technique,” IEEE J. Solid-State Circuits, vol. SC-16, pp. 708–715, Dec. 1981.
18. F. F. Yassa and S. G. Garverick, “A multichannel digital demodulator for LVDT/RDVT position sensors,” IEEE J. Solid-State Circuits, vol. 25, no. 2, pp. 441–450, Apr. 1990.
19. D. G. Haigh and B. Singh, “A switching scheme for switched capacitor filters which reduces the effect of parasitic capacitance associated with switch control terminals,” in Proc. IEEE Int. Symp. Circuits Syst., May 1983, pp. 586–589.
20. J. C. Candy, “A use of double integration in sigma delta modulation,” IEEE Trans. Commun., vol. COM-33, no. 3, pp. 249–258, Mar. 1985.