The Effect of Temperature on Single-Particle Latchup

IEEE Transactions on Nuclear Science

Volumn 38, Issue 6, 1991, Pages 1435-1441

  Johnston, A H ^a   Hughlock, B W ^a   Baze, M P ^a   Plaag, R E ^a  

^a BOEING COMPANY   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

DATA STORAGE, DIGITAL--RANDOM ACCESS; LASER BEAMS--APPLICATIONS; THERMAL EFFECTS;

LINEAR ENERGY TRANSFER; SINGLE PARTICLE LATCHUP;

INTEGRATED CIRCUITS, CMOS;

EID: 0026370425     PISSN: 00189499     EISSN: 15581578     Source Type: Journal    
DOI: 10.1109/23.124129     Document Type: Article

References (15)

1. W. Kolasinski, R. Koga, E. Schnauss and J. Duffey, “The Effect of Elevated Temperature on Latchup and Bit Errors in CMOS Devices,” IEEE Trans. Nucl. Sci., NS-33, 1605 (1986).
2. M. Shoga and D. Binder, “Theory of Single Event Latchup in Complementary Metal-Oxide Integrated Circuits,” IEEE Trans. Nucl. Sci., NS-33, 1714 (1986).
3. L. S. Smith, et al., “Temperature and Epi Thickness Dependence of the Heavy Ion Induced Latchup Thrheshold for a CMOS/EPI 16K Static RAM,” IEEE Trans. Nucl. Sci., NS-34, 1800 (1987).
4. D. Nicholls, et al., “Full Temperature Characterization of Two Microprocessor Technologies,” IEEE Trans. Nucl. Sci., NS-35, 1619 (1988).
5. R. Fang and J. Moll, “Latchup Model for the Parasitic p-n-p-n Path in Bulk CMOS,” IEEE Trans. Elect. Dev., ED-31, 113 (1984).
6. W. Stapor, et al., “Single Event Upset on Temperature for an NMOS/Resistive Load RAM,” IEEE Trans. Nucl. Sci., NS-33, 1610 (1986).
7. W. C. Dash and R. Newman, “Intrinsic Optical Absorption in Single Crystal Germanium and Silicon at 77 K and 300 K,” Phys. Rev., 22, 1151 (1955).
8. F. B. McLean and T. R. Oldham, “Charge Funneling in N-and P-Type Type Substrates,” IEEE Trans. Nucl. Sci., NS-29, 2018 (1982).
9. A. H. Johnston and B. W. Hughlock, “Latchup in CMOS from Single Particles,” IEEE Trans, Nucl. Sci., NS-37, 1886 (1990).
10. R. Rung and H. Momose, “DC Holding and Dynamic Triggering Characteristics of Bulk CMOS Latchup,” IEEE Trans. Elect. Dev., ED-30, 1647 (1983).
11. R.N.D.Arora, J.R. Hauser, and D.J. Roulston, IEEE Trans. Elect. Dev., ED-29, 292 (1982)
12. T. Aoki, “Dynamics of Heavy-Ion Latchup in CMOS Structures,” IEEE Trans. Elect. Dev., ED-35, 1835 (1988).
13. D. Takacs, et al., “Comparison of Latchup in p-and n-Well CMOS Circuits,” IEDM Technical Digest, 159, December, 1983.
14. T. Chapus, H. Constans Erems, and L. Rozier, “Latchup on CMOS/EPI Devices”, IEEE Trans. Nuc. Sci., NS-37, 1839 (1990).
15. H. Sichijo, “A Re-Examination of Practical Performance Limits of Scaled n-Channel and p-Channel MOS Devices for VLSI,” Solid St. Elect., 10, 969 (1983).