Framework for architecture synthesis of data conversion systems employing binary-weighted capacitor arrays

Proceedings - IEEE International Symposium on Circuits and Systems

Volumn 3, Issue , 1991, Pages 1789-1792

  Horta, N C ^a   Franca, J E ^a   Leme, C A ^a  

^a NONE

Author keywords

[No Author keywords available]

Indexed keywords

DATA CONVERSION, ANALOG TO DIGITAL - COMPUTER AIDED DESIGN; DATA CONVERSION, DIGITAL TO ANALOG - COMPUTER AIDED DESIGN; DATA CONVERSION, DIGITAL TO ANALOG - SYNTHESIS; INTEGRATED CIRCUITS, VLSI - COMPUTER AIDED DESIGN; INTEGRATED CIRCUITS, VLSI - SYNTHESIS;

BINARY WEIGHTED CAPACITOR ARRAYS; CALIBRATION NETWORKS; CAPACITOR ARRAYS;

DATA CONVERSION, ANALOG TO DIGITAL;

EID: 0026368739     PISSN: 02714310     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (13)