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Volumn , Issue , 1991, Pages 46-55

A conflict-free memory design for multiprocessors

(2)  Shing, Honda a   Ni, Lionel M a  

a NONE

Author keywords

[No Author keywords available]

Indexed keywords

COMPUTER ARCHITECTURE; COMPUTERS, SUPERCOMPUTER; DATA STORAGE, DIGITAL; SYNCHRONIZATION;

EID: 0026308847     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1145/125826.125868     Document Type: Conference Paper
Times cited : (4)

References (11)
  • 1
    • 85143044422 scopus 로고
    • Massachusetts, Cambridge
    • Inside the TC2000 Computer 1990 Massachusetts, Cambridge BBN Advanced Computers Inc.
    • (1990)
  • 3
    • 85143041912 scopus 로고
    • Experimental Parallel Computing Architectures
    • An introduction to the IBM research parallel processor prototype (RP3) Elsevier Science Publishers B.V. Amsterdam
    • G. F. Pfister Experimental Parallel Computing Architectures 123 140 1987 Elsevier Science Publishers B.V. Amsterdam An introduction to the IBM research parallel processor prototype (RP3)
    • (1987) , pp. 123-140
    • Pfister, G.F.1
  • 5
    • 0023560346 scopus 로고
    • Vector access performance in parallel memories using a skewed storage scheme
    • D. T. Harper J. R. Jump Vector access performance in parallel memories using a skewed storage scheme IEEE Transactions on Computers C-36 1440 1449 Dec. 1987
    • (1987) IEEE Transactions on Computers , vol.C-36 , pp. 1440-1449
    • Harper, D.T.1    Jump, J.R.2
  • 6
    • 0024666942 scopus 로고
    • An aperiodic storage scheme to reduce memory conflicts in vector processors
    • S. Weiss An aperiodic storage scheme to reduce memory conflicts in vector processors Proceedings of the International Symposium on Computer Architecture 380 385 Proceedings of the International Symposium on Computer Architecture 1989
    • (1989) , pp. 380-385
    • Weiss, S.1
  • 7
    • 85143023296 scopus 로고
    • OMP: A RISC-based multiprocessor using orthogonal-access memories and multiple spanning buses
    • K. Hwang OMP: A RISC-based multiprocessor using orthogonal-access memories and multiple spanning buses Proceedings of the ACM International Conference On Supercomputing Proceedings of the ACM International Conference On Supercomputing Amsterdam The Netherlands 1990-June
    • (1990)
    • Hwang, K.1
  • 8
    • 84939323181 scopus 로고
    • Line (block) size choice for CPU cache memories
    • A. Smith Line (block) size choice for CPU cache memories IEEE Transactions on Computers C-36 1063 1075 Sept. 1987
    • (1987) IEEE Transactions on Computers , vol.C-36 , pp. 1063-1075
    • Smith, A.1
  • 9
    • 0016624050 scopus 로고
    • Access and alignment of data in an array processor
    • D. H. Lawrie Access and alignment of data in an array processor IEEE Transactions on Computers C-24 1145 1155 Dec. 1975
    • (1975) IEEE Transactions on Computers , vol.C-24 , pp. 1145-1155
    • Lawrie, D.H.1
  • 10
    • 0022598998 scopus 로고
    • Memory access buffering in multiprocessors
    • M. Dubois C. Scheurich F. Briggs Memory access buffering in multiprocessors Proceedings of the 13th Annual International Symposium on Computer Architecture 434 442 Proceedings of the 13th Annual International Symposium on Computer Architecture 1986-June
    • (1986) , pp. 434-442
    • Dubois, M.1    Scheurich, C.2    Briggs, F.3
  • 11
    • 0025532026 scopus 로고
    • Resource binding—a universal approach to parallel programming
    • H. Shing L. M. Ni Resource binding—a universal approach to parallel programming Proceedings of Supercomputing '90 Conference 574 583 Proceedings of Supercomputing '90 Conference 1990-Nov.
    • (1990) , pp. 574-583
    • Shing, H.1    Ni, L.M.2


* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.