Merged BiCMOS Logic to Extend the CMOS/BiCMOS Performance Crossover Below 2.5-V Supply

IEEE Journal of Solid-State Circuits

Volumn 26, Issue 11, 1991, Pages 1606-1614

  Ritts, Rosalyn B ^a   Plummer, James D ^a   Saraswat, Krishna C ^a   Raje, Prasad A ^a,b   Cham, Kit M ^c  

^a STANFORD UNIVERSITY   (United States)

^b HEWLETT PACKARD LABORATORIES   (United States)

^c HEWLETT PACKARD COMPANY   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

INTEGRATED CIRCUIT MANUFACTURE; INTEGRATED CIRCUITS, CMOS--PERFORMANCE;

BICMOS LOGIC;

LOGIC DEVICES;

EID: 0026257211     PISSN: 00189200     EISSN: 1558173X     Source Type: Journal    
DOI: 10.1109/4.98979     Document Type: Article

References (15)

1. R. B. Ritts and J. D. Plummer, “Merged BiCMOS with vertical PNP,” in Device Res. Conf. Dig. Tech. Papers, 1990, p. IIB-8.
2. S. Ogura et al., “Merged complementary BiCMOS for logic applications,” in Symp. VLSI Technology Tech. Dig., 1990, pp. 81–82.
3. T. Hanibuchi, M. Ueda, K. Higashitani, M. Hatanaka, and K. Mashiko, “A bipolar-PMOS merged basic cell for 0.8 μ m BiCMOS sea of gates,” in Proc. IEEE Custom Integrated Circuits Conf., 1990, p. 4.2.1.
4. J. B. Kuo, G. P. Rosseel, and R. W. Dutton, “Two-dimensional analysis of a merged BiPMOS device,” IEEE Trans. Computer-Aided Design, vol. 8, pp. 929–932, Aug. 1989.
5. H. Momose et al., “Characterization of speed and stability of BiNMOS gates with a bipolar and PMOSFET merged structure,” in IEDM Tech. Dig., 1990, pp. 231–232.
6. P. Raje, R. Ritts, K. Cham, J. Plummer, and K. Saraswat, “MBiCMOS: A device and circuit technique scalable to sub-micron, sub-2V regime,” in ISSCC Dig. Tech. Papers, 1991.
7. C. Chen, “Level-shifted and voltage reduced 0.5 μ m BiCMOS circuits,” in ISSCC Dig. Tech. Papers, 1990, pp. 236–237.
8. Y. Nishio et al., “A BiCMOS logic gate with positive feedback,” in ISSCC Dig. Tech. Papers, 1989, pp. 116–117.
9. H.J. Shin et al., “Full-swing complementary BiCMOS logic circuits,” in Bipolar Circuits and Technology Meeting Tech. Dig., 1989, pp. 229–233.
10. A. Watanabe, T. Nagano, S. Shukuri, and T. Ikeda, “Future Bi-CMOS technology for scaled supply voltage,” in IEDM Tech. Dig., 1989, pp. 429–432.
11. S. C. Lee and D. W. Schucker, “BiCMOS driver circuit,” U.S. Patent 4 616 146, Oct. 7, 1986.
12. E. W. Greeneich and K. L. McLaughlin, “Analysis and characterization of BiCMOS for high-speed digital logic,” IEEE J. Solid-State Circuits, vol. 23, pp. 558–565, Apr. 1988.
13. G. P. Rosseel and R. W. Dutton, “Influence of device parameters on the switching speed of BiCMOS buffers,” IEEE J. Solid-State Circuits, vol. 24, pp. 90–99, Feb. 1989.
14. J. Shott, C. Knorr, and M. Prisbe, “BiCMOS technology overview,” Center for Integrated Systems, Stanford, CA, Stanford BiCMOS Project Tech. Rep., Sept. 1990.
15. P. Raje, K. Saraswat, and K. Cham, “A new BiCMOS/CMOS gate comparison/design methodology and supply voltage scaling model,” in IEDM Tech. Dig., 1989, pp. 433–436.