Parametric yield optimization of CMOS analogue circuits by quadratic statistical circuit performance models

International Journal of Circuit Theory and Applications

Volumn 19, Issue 6, 1991, Pages 579-592

  Yu, T K ^a,c   Kang, S M ^a   Sacks, J ^a   Welch, W J ^b  

^a UNIVERSITY OF ILLINOIS AT URBANA CHAMPAIGN   (United States)

^b UNIVERSITY OF WATERLOO   (Canada)

^c MOTOROLA INC   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

COMPUTER SIMULATION; OPTIMIZATION; STATISTICAL METHODS;

CMOS ANALOG CIRCUITS; PARAMETRIC YIELD; QUADRATIC MODELS; STATISTICAL CIRCUIT DESIGN;

INTEGRATED CIRCUITS, CMOS;

EID: 0026256867     PISSN: 00989886     EISSN: 1097007X     Source Type: Journal    
DOI: 10.1002/cta.4490190606     Document Type: Article

References (18)

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