Test generation, design-for-testability and built-in self-test for arithmetic units based on graph labeling

Journal of Electronic Testing

Volumn 2, Issue 4, 1991, Pages 351-372

  Chatterjee, Abhijit ^a   Abraham, Jacob A ^b  

^a GE GLOBAL RESEARCH   (United States)

^b UNIVERSITY OF TEXAS AT AUSTIN   (United States)

Author keywords

Built in self test; design for testability; iterative logic array; pseudo exhaustive test; test generation

Indexed keywords

AUTOMATIC TESTING; MATHEMATICAL TECHNIQUES - ITERATIVE METHODS;

ARITHMETIC FUNCTIONS; BUILT-IN SELF-TESTS; DESIGN-FOR-TESTABILITY; ITERATIVE LOGIC ARRAYS;

LOGIC CIRCUITS;

EID: 0026255894     PISSN: 09238174     EISSN: 15730727     Source Type: Journal    
DOI: 10.1007/BF00135230     Document Type: Article

References (29)

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