Fast clock synchroniser using initial phase presetting DPLL (IPP-DPLL) for burst signal reception

Electronics Letters

Volumn 27, Issue 21, 1991, Pages 1902-1904

  Ohno, K ^a   Adachi, D ^a  

^a NTT CORPORATION   (Japan)

Author keywords

Circuit design; Digital communication systems

Indexed keywords

DIGITAL COMMUNICATION SYSTEMS; PHASE MODULATION--PHASE SHIFT KEYING;

CLOCK SYNCHRONIZERS; QDPSK; SIGNAL RECEPTION;

SIGNAL RECEIVERS;

EID: 0026240425     PISSN: 00135194     EISSN: None     Source Type: Journal    
DOI: 10.1049/el:19911181     Document Type: Article

References (2)

1. Lindsey, W. C., and Chie, C. M.: ‘A survey of digital phase-locked loop’, Proc. Ieee, April 1981, 69, pp. 410–431
2. Ohno, K., and Adachi, F.: ‘Effects of postdetection selection diversity reception in QDPSK land mobile radio’, Electron. Lett., September 1989, 25, pp. 1293–1294