Bit-level systolic arrays for modular multiplication

Journal of VLSI Signal Processing

Volumn 3, Issue 3, 1991, Pages 215-223

  Koç, Çetin K ^a   Hung, Ching Yu ^a  

^a UNIVERSITY OF HOUSTON   (United States)

Author keywords

carry save adders; modular multiplication; scheduling; sign estimation; systolic array

Indexed keywords

COMPUTER ARCHITECTURE; COMPUTER METATHEORY; COMPUTERS, DIGITAL--ADDERS; MATHEMATICAL TECHNIQUES;

MODULAR MULTIPLICATION; SYSTOLIC ARRAYS;

COMPUTER PROGRAMMING;

EID: 0026226404     PISSN: 09225773     EISSN: 1573109X     Source Type: Journal    
DOI: 10.1007/BF00925832     Document Type: Article

References (18)

1. A method for obtaining digital signatures and public-key cryptosystems
2. An NMOS implementation of a large number modulo multiplier for data encryption systems
3. A computer algorithm for the product AB modulo M
4. Comments on: ‘A computer algorithm for the product AB modulo M.’
5. Fast computation of A*B modulo N
6. Multi-operand modulo addition using carry save adders
7. Carry save adders for computing the product AB modulo N
8. A survey of hardware implementations of RSA
9. Parallel algorithms and systolic arrays designs for RSA cryptosystem
10. A fast modular multiplication algorithm with application to two key cryptography
11. Carry delayed save adders for computing the product AB modulo N in log2N steps