A Novel Architecture for Queue Management in the ATM Network

IEEE Journal on Selected Areas in Communications

Volumn 9, Issue 7, 1991, Pages 1110-1118

  Chao, H Jonathan ^a  

^a TELCORDIA TECHNOLOGIES   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

COMPUTER SIMULATION; DATA TRANSMISSION - PACKET SWITCHING; MICROPROCESSOR CHIPS; PROBABILITY - QUEUEING THEORY; TELECOMMUNICATION - TRAFFIC;

ASYNCHRONOUS TRANSFER MODE; ATM NETWORK QUEUE MANAGEMENT; LONG-BURST TRAFFIC; VLSI SEQUENCER CHIP; WIDEBAND INTEGRATED NETWORKS;

COMPUTER NETWORKS;

EID: 0026226378     PISSN: 07338716     EISSN: None     Source Type: Journal    
DOI: 10.1109/49.103556     Document Type: Article

References (14)

1. CCITT SG XVIII Draft Recommendation 1.150, “BISDN ATM functional characteristics,” Geneva, Switzerland, May 1990.
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5. H. J. Chao, “A distributed modular Terabit/sec ATM switch,” in Proc. IEEE GLOBECOM’90, San Diego, CA, Dec. 1990, pp. 1594-1601; also to appear in IEEE J. Select. Areas Commun., Oct. 1991.
6. Y. S. Yeh, M. G. Hluchyj, and A. S. Acampora, “The knockout switch: A simple architecture for high-performance packet switching,” IEEE J. Select. Areas Commun., vol. 5, no. 8, pp. 1274–1283, Oct. 1987.
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8. A. Demers, S. Keshav, and S. Shenker, “Analysis and simulation of a fair queueing algorithm,” presented at SIGCOMM’89,1989.
9. S. P. Morgan, “Queueing disciplines and passive congestion control in byte-stream networks,” in Proc. IEEE INFOCOM’89, 1989, pp. 711–720.
10. M. G. H. Katevenis, “Fast switching and fair control of congested flow in broadband networks,” IEEE J. Select. Areas Commun., vol. 5, no. 8, pp. 1315–1326, Oct. 1987.
11. L. Zhang, “VirtualClock: A new traffic control algorithm for packet switching networks,” in Proc. SIGCOMM’90, Philadelphia, PA, Sept. 1990, pp. 19–29.
12. T. Eliazov, V. Ramaswami, and W. Willinger, “Performance of an ATM switch: Simulation study,” in Proc. IEEE INFOCOM’90, San Francisco, CA, June 1990, pp. 664–659.
13. A. Lyengarand M. E. Zarki, “Switched prioritized packets,” in Proc. IEEE GLOBECOM’89, Dallas, TX, Nov. 1989, pp. 1181–1186.
14. H. J. Chao, “Parallel/pipeline VLSI computing structures for robotic applications,” Ph.D. dissertation, The Ohio State University, Columbus, OH, May 1985.