Design of Submicrometer CMOS Differential Pass-Transistor Logic Circuits

IEEE Journal of Solid-State Circuits

Volumn 26, Issue 9, 1991, Pages 1249-1258

  Pasternak, John H ^a  

^a UNIVERSITY OF TORONTO   (Canada)

Author keywords

[No Author keywords available]

Indexed keywords

ELECTRONIC CIRCUITS, BUFFER - DESIGN; INTEGRATED CIRCUITS, CMOS - DESIGN; MICROELECTRONICS - NOISE, SPURIOUS SIGNAL;

CMOS LOGIC CIRCUITS; DIFFERENTIAL PASS TRANSISTOR LOGIC; SUBMICRON DEVICES;

LOGIC CIRCUITS;

EID: 0026220947     PISSN: 00189200     EISSN: 1558173X     Source Type: Journal    
DOI: 10.1109/4.84941     Document Type: Article

References (8)

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2. J. H. Pasternak and C. A. T. Salama, “Optimization of submicron CMOS differential pass-transistor logic,” in Proc. ESSCIRC (Vienna, Austria), 1989, pp. 218–221.
3. J. H. Pasternak and C. A. T. Salama, “Differential pass-transistor logic partial-product generator for iterative multipliers,” in Proc. ECCTD (Brighton, U.K.), 1989, pp. 176–179.
4. K. Yano et al., “A 3.8ns CMOS 16 × 16 multiplier using complementary pass transistor logic,” in Proc. CICC (San Diego, CA), 1989.
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8. M. Shoji, CMOS Digital Circuit Technology. Englewood Cliffs, NJ: Prentice-Hall, 1988.