Design of Robustly Testable Combinational Logic Circuits

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems

Volumn 10, Issue 8, 1991, Pages 1036-1048

  Kundu, Sandip ^a   Reddy, Sudhakar M ^b   Jha, Niraj K ^c  

^a IBM T J WATSON RESEARCH CENTER   (United States)

^b UNIVERSITY OF IOWA   (United States)

^c PRINCETON UNIVERSITY   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

INTEGRATED CIRCUIT TESTING; INTEGRATED CIRCUITS, CMOS - COMPUTER AIDED DESIGN;

CMOS LOGIC; DESIGN FOR TESTABILITY; MULTILEVEL CIRCUITS; PATH DELAY FAULTS; ROBUST TESTABILITY; STUCK OPEN FAULTS;

LOGIC CIRCUITS, COMBINATORIAL;

EID: 0026205216     PISSN: 02780070     EISSN: 19374151     Source Type: Journal    
DOI: 10.1109/43.85740     Document Type: Article

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