A Cv Technique for Measuring Thin Soi Film Thickness

IEEE Electron Device Letters

Volumn 12, Issue 8, 1991, Pages 453-455

  Chen, Jian ^a   Solomon, Ray ^a   Chan, Tung Yi ^a   Ko, Ping Keung ^b   Hu, Chenming ^c  

^a UNIVERSITY OF CALIFORNIA   (United States)

^b INTEL CORPORATION   (United States)

^c CYPRESS SEMICONDUCTOR   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

ELECTRIC MEASUREMENTS - CAPACITANCE; SEMICONDUCTOR DEVICES - THIN FILMS; SEMICONDUCTOR DEVICES, MOSFET - APPLICATIONS;

CMOS TECHNOLOGY; CV TECHNIQUE; GATE-SOURCE/DRAIN MEASUREMENTS; N-CHANNEL MOSFET'S; SIMOX WAFERS; THIN SOI FILM THICKNESS MEASUREMENT;

SEMICONDUCTOR DEVICE MANUFACTURE;

EID: 0026204649     PISSN: 07413106     EISSN: 15580563     Source Type: Journal    
DOI: 10.1109/55.119163     Document Type: Article

References (6)

1. J.-P. Colinge, “Reduction of kink effect in thin-film SOI MOSFET's,” IEEE Electron Device Lett., vol. 9, no. 2, p. 97, 1988.
2. J. Whitfield and S. Thomas, “An electrical method to measure SOI film thickness,” IEEE Electron Device Lett., vol. EDL-7, no. 6, p. 347, 1986.
3. D.-P. Vu, private communication.
4. M. Hoand and M. Tack, “Rapid electrical measurements of back oxide and silicon film thickness in an SOI CMOS process,” IEEE Trans. Electron Devices, vol. 38, no. 3, p. 647, 1991.
5. F. Assaderahhi et al., “Transient behavior of subthreshold characteristics of fully depleted SOI MOSFET's,” submitted to IEEE Electron Device Lett.
6. M.-S. Liang, J. Y. Choi, P.-K. Ko, and C. Hu, “Inversion-layer capacitance and mobility of very thin gate-oxide MOSFET's,” IEEE Trans. Electron Devices, vol. ED-33, no. 3, p. 409, 1984.