A Hybrid Number System Processor with Geometric and Complex Arithmetic Capabilities

IEEE Transactions on Computers

Volumn 40, Issue 8, 1991, Pages 952-962

  Lai, Fang Shi ^a   Eric Wu, Ching Farn ^a  

^a IBM T J WATSON RESEARCH CENTER   (United States)

Author keywords

Algorithm; architecture; data conversion; digital signal processing; floating point; hybrid number system; logarithmic number system; multiplier; processor

Indexed keywords

COMPUTER PROGRAMMING - ALGORITHMS; COMPUTER SIMULATION; INTEGRATED CIRCUITS, CMOS; MATHEMATICAL TRANSFORMATIONS - FAST FOURIER TRANSFORMS;

ARITHMETIC PROCESSORS; COPROCESSORS; FLOATING POINT ARITHMETIC; LOGARITHMIC ARITHMETIC;

SIGNAL PROCESSING;

EID: 0026202969     PISSN: 00189340     EISSN: None     Source Type: Journal    
DOI: 10.1109/12.83639     Document Type: Article

References (27)

1. B. C. Cole, “Signal processing: a big switch to digital,” Electronics, pp. 42-46, 1985.
2. A. V. Oppenhein and R. W. Schafer, Digital Signal Processing. Englewood Cliffs, NJ: Prentice-Hall, 1975.
3. H. Yoshimura, T. Nakanishi, and H. Tamauchi, “A 50 Mhz CMOS geometrical mapping processor,” Tech. Dig. ISSCC, pp. 162-163, 1988.
4. Y. Hagiwara et al., “A single chip digital signal processor and its application to real time speech analysis,” IEEE Trans. Acoust., Speech, Signal Processing, Vol. ASSP-31, pp. 339-346, 1983.
5. B. C. Cole, “Motorola's new DSP engine comes with floating-point,” Electronics, pp. 64-65, 1988.
6. J. H. Lang, C. A. Zukowski, R. O. LaMaire, and C. H. An, “Integrated-circuit logarithmic arithmetic units,” IEEE Trans. Comput., Vol. C-34, pp. 475-482, 1985.
7. G. L. Sicuranza, “On efficient implementations of 2-D digital filters using logarithmic number system,” IEEE Trans. Acoust., Speech, Signal Processing, Vol. ASSP-31, pp. 877-885, 1983.
8. T. Kurokawa, J. A. Paynes, and S. C. Lee, “Error analysis of recursive digital filters implemented with logarithmic number system,” IEEE Trans. Acoust., Speech, Signal Processing, Vol. ASSP-28, pp. 706-715, 1980.
9. E. E. Swartzlander et al., “Sign/logarithm arithmetic for FFT implementation,” IEEE Trans. Comput, Vol. C-32, pp. 526-534, 1983.
10. E. E. Swartzlander and A. G. Alexopoulos, “The sign/logarithm number system,” IEEE Trans. Comput., Vol. C-24, pp. 1238-1242, 1975.
11. E. L. Hall, D. D. Lynch, and S.J. Dwyer III, “Generation of products and quotients using approximate binary logarithms for digital filtering applications,” IEEE Trans. Comput., Vol. C-19, pp. 97-105, 1970.
12. M. Combet, H. Van Zonneveld, and L. Verbeek, “Computation of the base two logarithm of binary number,” IEEE Trans. Electron. Comput., Vol. EC-14, pp. 363-367, 1965.
13. D. Marino, “New algorithms for the approximation evaluation in hardware of binary logarithms and elementary functions,” IEEE Trans. Comput., Vol. C-21, pp. 1416-1421, 1972.
14. T. A. Brubaker and J. C. Becker, “Multiplication using logarithms implemented with read-only memory,” IEEE Trans. Comput., Vol. C-24, pp. 761-765, 1975.
15. H. Y. Lo and Y. Aoki, “Generation of a precise binary logarithm with difference grouping programmable logic array,” IEEE Trans. Comput., Vol. C-34, pp. 681-691, 1985.
16. F. J. Taylor, “An extended precision logarithmic number system,” IEEE Trans. Acoust., Speech, Signal Processing, Vol. ASSP-31, pp. 231-233, 1983.
17. M. G. Arnold, J. Cowles, and T. Bailey, “Improved accuracy for logarithmic addition in DSP applications,” Tech. Dig. ICASSP, pp. 1714-1717, 1988.
18. F. J. Taylor, “A hybrid floating-point logarithmic number system processor,” IEEE Trans. Circuits Syst., Vol. CAS-32, pp. 92-95, 1985.
19. J. P. Hayes, Computer Architecture and Organization. New York: McGraw-Hill, 1988.
20. F. J. Taylor, R. Gill, J. Joseph, and J. Radke, “A 20 bit logarithmic number system processor,” IEEE Trans. Comput., Vol. C-37, pp. 190-200, 1988.
21. A. S. Noetzel, “An interpolating memory unit for function evaluation: Analysis and design,” IEEE Trans. Comput, Vol. C-38, pp. 377-384, 1989.
22. W. A. Perera, “Architecture for multiplierless fast Fourier transform hardware implementation in VLSI,” IEEE Trans. Acoust, Speech, Signal Processing, Vol. ASSP-35, pp. 1750-1760, 1987.
23. B. Barazesh, J. C. Michalina, and A. Picco, “A VLSI signal processor with complex arithmetic capability,” IEEE Trans. Circuits Syst., Vol. 35, pp. 495-505, 1988.
24. B. Eichen, “NEC's μPD77230 digital signal processor,” IEEE Micro, pp. 60-69, 1986.
25. J. E. Voider, “The CORDIC trigonometric computing techniques,” IRE Trans. Electron. Comput, Vol. EC-8, pp. 330-334, 1959.
26. F. S. Lai, “Design of a 100 MHz hybrid number system data execution unit,” in 1990 Symp. VLSI Circuits, Dig. Tech. Papers, Honolulu, HI, pp. 121-122, 1990.
27. F. S. Lai, “A 10-ns hybrid number system data execution unit for digital signal processing systems,” IEEE J. Solid-State Circuits, Vol. SC-26, pp. 590-599, 1991.