Interconnection Delay in Very Highspeed VLSI

IEEE Transactions on Circuits and Systems

Volumn 38, Issue 7, 1991, Pages 779-790

  Zhou, Dian ^a   Preparata, Franco P ^a   Kang, S M ^a  

^a UNIVERSITY OF ILLINOIS AT URBANA CHAMPAIGN   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

ELECTRIC NETWORKS - TRANSMISSION LINE THEORY; INTEGRATED CIRCUITS, VLSI; MATHEMATICAL TECHNIQUES - EIGENVALUES AND EIGENFUNCTIONS; MATHEMATICAL TRANSFORMATIONS - LAPLACE TRANSFORMS;

RC DELAY DOMAIN; TRANSMISSION-LINE DELAY DOMAIN; TRANSMSSION LINE MODEL; VERY-HIGH-SPEED VLSI; VLSI INTERCONNECTION DELAYS;

INTEGRATED CIRCUITS, DIGITAL;

EID: 0026190523     PISSN: 00984094     EISSN: None     Source Type: Journal    
DOI: 10.1109/31.135749     Document Type: Article

References (15)

1. G. Bilardi, M. Pracchi, and F.P. Preparata, “A critique of network speed in VLSI models of computation,” IEEE J. SolidState Circuits, vol. SC-17, pp. 696–702, Aug. 1982.
2. H.B. Bakoglu and J.D. Meindl, “Optimal interconnection circuits for VLSI,” IEEE Trans. Electron Devices, vol. ED-32, pp. 903–909, May 1985.
3. K.C. Saraswat and F. Mohammadi, “Effect of scaling of interconnections on the time delay of VLSI circuits,” IEEE J. SolidState Circuits, SC-17, pp. 442–448, June 1982.
4. H. Hasegawa, M. Furukawa, and H. Yanai, “Properties of microstrip lines on Si-SiOz system,” IEEE Trans. Microwave Theory Tech., vol. MIT-19, pp. 869–881, Nov. 1971.
5. V. Milutinovic, “GaAs microprocessor technology,” IEEE Computer, vol. 19, Oct., 1986.
6. B.K. Gilbert et al., “Signal processors based upon GaAs ICs: The need for a holistic design approach,” IEEE Computer, vol. 19, Oct. 1986.
7. T. Sakurai and K. Tamaru, “Simple formulas for two- and three-dimensional capacitances,” IEEE Trans. Electron Devices, vol. ED-30, pp. 183–185, Feb. 1983.
8. R.H. Dennard et al., “Design of ion implanted MOSFET's with very small physical dimensions,” IEEE J. SolidState Circuits, SC-9, pp. 256–268, 1974.
9. T. Sakurai, “Approximation of wiring delay in MOSFET IC LSI,” IEEE J. SolidState Circuits, vol. SC-18, pp. 418–426, Aug. 1983.
10. H.B. Bakoglu, J.T. Walker, and J.D. Meindl, “A symmetric clock-distribution tree and optimized highspeed interconnections for reduced clock skew in ULSI and WSI circuits,” in Proc. Int. Conf. Computer Design, pp. 118–122, Oct. 1986.
11. J.Y. Chen, “CMOS-The emerging VLSI technology,” IEEE Circuits and Devices Mag., pp. 16–31, Mar. 1986.
12. Y. Fukuoka, Y.C. Shin, and T. Itoh, “Analysis of slow-wave coplanar waveguide for monolithic integrated circuits,” IEEE Trans. Microwave Theory Tech., vol. MIT-31, pp. 567–573, July 1983.
13. D.S. Gao, A.T. Yang, and S.M. Kang, “Accurate modeling and simulation of parallel interconnection in highspeed integrated circuits,” in Proc. Int. Symp. Circuits and Systems, pp. 2105–2108, June 1988.
14. M. Cases and D. Quinn, “Transient response of uniformly distributed RLC transmission lines,” IEEE Trans. Circuits Syst., vol. CAS-27, pp. 200–207, Mar. 1980.
15. C. -K.C. Tzuang and T. Itoh, “highspeed pulse transmission along a slow-wave CPW for monolithic microwave integrated circuits,” IEEE Trans. Microwave Theory Tech., vol. 35, pp. 697–704, Aug. 1987.