High-Voltage Planar Devices Using Field Plate and Semi-Resistive Layers

IEEE Transactions on Electron Devices

Volumn 38, Issue 7, 1991, Pages 1681-1684

  Jaume, D ^a   Reynes, J M ^a   Charitat, G ^b   Rossel, P ^b  

^a MOTOROLA INC   (United States)

^b Laboratoire d’Automatique et d’Analyse des Systemes ^*  (France)

Author keywords

[No Author keywords available]

Indexed keywords

FILMS--DIELECTRIC; INDUSTRIAL ELECTRONICS--COMPONENTS; SOLID STATE DEVICES, THIN FILM;

HIGH VOLTAGE PLANAR DEVICES; HIGH VOLTAGE TRANSISTORS; PASSIVATION LAYER; POLYCRYSTALLINE SILICON; POWER SEMICONDUCTORS;

TRANSISTORS, BIPOLAR;

EID: 0026188096     PISSN: 00189383     EISSN: 15579646     Source Type: Journal    
DOI: 10.1109/16.85167     Document Type: Article

References (14)

1. B. J. Baliga, “High voltage device termination techniques,” Proc. Inst. Elec. Eng., pt. 1, vol. 129, no. 5, Oct. 1982. —, Modern Power Devices. New York: Wiley-Interscience, 1987.
2. T. Matsushita, A. Teruaki, O. Takaji, Y. Hisayoshi, H. Hisao, O. Masanori, and K. Yoshiyuki, “Highly reliable high-voltage transistors by use of SIPOS process,” IEEE Trans. Electron Devices, vol. ED-23, no. 8, pp. 826–830, Aug. 1976.
3. A. Mimura, M. Oohayashi, S. Murakami, and N. Momma, “High voltage planar structure using SiO 2 -SIP0S-SiO 2 film,” IEEE Electron Device Lett., vol. EDL-6, no. 4, Apr. 1985.
4. D. Jaume, A. Peyre-Lavigne, and G. Charitat, “High voltage semiconductor device and fabrication process,” US Patent 07 437 404, 1989.
5. D. Jaume, “Etude des gardes peripheriques des composants silicium planar haute-tension en technologie SIPOS,” Ph.D. dissertation, Toulouse, 1990.
6. F. Conti and M. Conti, “Surface breakdown in silicon planar diodes equipped with field plate,” Solid-State Electron., vol. 15, pp. 93–105, 1972.
7. G. Charitat, P. Rossel, M. Gharbi, A. Nezzar, and P. Granadel, “BIDIM2: Software tool for power and high voltage devices electrical simulation,” in 3rd Symp. on Electronic for Telecommunications (Porto, Portugal, May 4–6, 1988), pp. C8.5-8.7.
8. S. M. Sze, Physics of Semiconductor Devices, 2nd ed. New York: Wiley, 1981.
9. R. Van Overstraeten and H. De Man, “Measurement of the ionization rates in diffused silicon p-n junctions,” Solid-State Electron., vol. 13, pp. 583–608, 1970.
10. M. L. Tarng, “Carrier transport in oxygen-rich polycrystalline-sili-con films,” J. Appl. Phys., vol. 49, no. 7, July 1978.
11. G. Charitat, D. Jaume, A. Peyre-Lavigne, and P. Rossel, “1000 and 1500 volts planar devices using field plate and semi-resistive layers: Design and fabrication,” presented at IEDM, San Francisco, CA, Dec. 1990.
12. H. K. Gummel, “A charge control relation for bipolar transistors,” Bell Syst. Tech. J., vol. 49, p. 115, 1970.
13. G. F. Cerofolini and M. L. Polognano, “Residual non-idealities in the almost ideal silicon p-n junction,” Appl. Phys., vol. A-50, pp. 273–286, 1990.
14. V. Boisson, “Etude de la geometrie optimale des peripheries des jonctions planars,” Ph.D. dissertation, ECL 85–05, Apr. 1985.