메뉴 건너뛰기




Volumn 10, Issue 7, 1991, Pages 895-903

A New Methodology for the Design Centering of IC Fabrication Processes

Author keywords

[No Author keywords available]

Indexed keywords

COMPUTER SIMULATION; INTEGRATED CIRCUITS, CMOS - MANUFACTURE;

EID: 0026186319     PISSN: 02780070     EISSN: 19374151     Source Type: Journal    
DOI: 10.1109/43.87599     Document Type: Article
Times cited : (35)

References (20)
  • 1
    • 0024906277 scopus 로고
    • Design for manufacturability and yield
    • June
    • A. J. Strojwas, “Design for manufacturability and yield,” in Design Automation Conf. Proc. 1989, June 1989, pp. 454–459.
    • (1989) Design Automation Conf. Proc. , pp. 454-459
    • Strojwas, A.J.1
  • 2
    • 84944982891 scopus 로고
    • A survey of optimization techniques for integrated-circuit design
    • Oct.
    • R. K. Brayton, G. D. Hachtel, and A. L. Sangiovanni-Vincentelli, “A survey of optimization techniques for integrated-circuit design,’ Proc. IEEE, vol. 69, pp. 1334–1362, Oct. 1981.
    • (1981) Proc. IEEE , vol.69 , pp. 1334-1362
    • Brayton, R.K.1    Hachtel, G.D.2    Sangiovanni-Vincentelli, A.L.3
  • 3
    • 0022603501 scopus 로고
    • A methodology for worst-case analysis of integrated circuits
    • Jan.
    • S. R. Nassif, A. J. Strojwas, and S. W. Director, “A methodology for worst-case analysis of integrated circuits,” IEEE Trans. Computer-Aided Design, vol. CAD-5, pp. 104–113, Jan. 1986.
    • (1986) IEEE Trans. Computer-Aided Design , vol.CAD-5 , pp. 104-113
    • Nassif, S.R.1    Strojwas, A.J.2    Director, S.W.3
  • 4
    • 0021202647 scopus 로고
    • FABRICS-II: A statistical based IC fabrication process simulator
    • Jan.
    • S. R. Nassif, A. J. Strojwas, and S. W. Director, “FABRICS-II: A statistical based IC fabrication process simulator,” IEEE Trans. Computer-Aided Design, vol. CAD-3, pp. 40–46, Jan. 1984.
    • (1984) IEEE Trans. Computer-Aided Design , vol.CAD-3 , pp. 40-46
    • Nassif, S.R.1    Strojwas, A.J.2    Director, S.W.3
  • 5
    • 0022605091 scopus 로고
    • Parameter extraction for statistical IC process characterization
    • Jan.
    • C. J. Spanos and S. W. Director, “Parameter extraction for statistical IC process characterization,” IEEE Trans. Computer-Aided Design, vol. CAD-5, pp. 66–78, Jan. 1986.
    • (1986) IEEE Trans. Computer-Aided Design , vol.CAD-5 , pp. 66-78
    • Spanos, C.J.1    Director, S.W.2
  • 6
    • 0019246429 scopus 로고
    • Statistical exploration approach to design centering
    • part G, Dec.
    • R. S. Soin and R. Spence, “Statistical exploration approach to design centering,” Inst. Elec. Eng. Proc. part G, vol. 127, no. 6, pp. 260–269, Dec. 1980.
    • (1980) Inst. Elec. Eng. Proc. , vol.127 , Issue.6 , pp. 260-269
    • Soin, R.S.1    Spence, R.2
  • 7
    • 0019592219 scopus 로고
    • Statistical design centering and tolerancing using Parametric Sampling
    • July
    • K. Singhal and J. F. Pinel, “Statistical design centering and tolerancing using Parametric Sampling;” IEEE Trans. Circuits Syst., vol. CAS-28, pp. 692–701, July 1981.
    • (1981) IEEE Trans. Circuits Syst. , vol.CAS-28 , pp. 692-701
    • Singhal, K.1    Pinel, J.F.2
  • 8
    • 0020087855 scopus 로고
    • Design centering by yield prediction
    • Feb.
    • K. J. Antreich and R. K. Koblitz, “Design centering by yield prediction,” IEEE Trans. Circuits Syst., vol. CAS-29, pp. 88–96, Feb. 1982.
    • (1982) IEEE Trans. Circuits Syst. , vol.CAS-29 , pp. 88-96
    • Antreich, K.J.1    Koblitz, R.K.2
  • 9
    • 0021510833 scopus 로고
    • An extrapolated yield approximation technique for use in yield maximization
    • Oct.
    • D. E. Hocevar, M. R. Lightner, and T. N. Trick, “An extrapolated yield approximation technique for use in yield maximization,” IEEE Trans. Computer-Aided Design, vol. CAD-3, pp. 279–287, Oct. 1984.
    • (1984) IEEE Trans. Computer-Aided Design , vol.CAD-3 , pp. 279-287
    • Hocevar, D.E.1    Lightner, M.R.2    Trick, T.N.3
  • 10
    • 0017515253 scopus 로고
    • The simplicial approach to design centering
    • July
    • S. W. Director and G. D. Hachtel, “The simplicial approach to design centering,” IEEE Trans. Circuits Syst., vol. CAS-24, pp. 363–372, July 1977.
    • (1977) IEEE Trans. Circuits Syst. , vol.CAS-24 , pp. 363-372
    • Director, S.W.1    Hachtel, G.D.2
  • 11
    • 0019909459 scopus 로고
    • A design centering algorithm for nonconvex regions of acceptability
    • Jan.
    • L. M. Vidigal and S. W. Director, “A design centering algorithm for nonconvex regions of acceptability,” IEEE Trans. Computer-Aided Design, vol. CAD-1, pp. 13–24, Jan. 1982.
    • (1982) IEEE Trans. Computer-Aided Design , vol.CAD-1 , pp. 13-24
    • Vidigal, L.M.1    Director, S.W.2
  • 12
    • 0024029576 scopus 로고
    • Parametric yield optimization for MOS circuit blocks
    • June
    • D. E. Hocevar, P. F. Cox, and P. Yang, “Parametric yield optimization for MOS circuit blocks,” IEEE Trans. Computer-Aided Design, vol. 7, pp. 645–658, June 1988.
    • (1988) IEEE Trans. Computer-Aided Design , vol.7 , pp. 645-658
    • Hocevar, D.E.1    Cox, P.F.2    Yang, P.3
  • 13
    • 0024931842 scopus 로고
    • An efficient methodology for building macromodels of IC fabrication processes
    • Dec.
    • K. K. Low and S. W. Director, “An efficient methodology for building macromodels of IC fabrication processes,” IEEE Trans. Computer-Aided Design, vol. CAD-8, pp. 1299–1313, Dec. 1989.
    • (1989) IEEE Trans. Computer-Aided Design , vol.CAD-8 , pp. 1299-1313
    • Low, K.K.1    Director, S.W.2
  • 14
    • 25844525200 scopus 로고
    • A methodology for statistical integrated circuit process design
    • Carnegie Mellon Univ., Pittsburgh, PA, Apr.
    • K. K. Low, “A methodology for statistical integrated circuit process design,” Ph.D. dissertation, Carnegie Mellon Univ., Pittsburgh, PA, Apr. 1989.
    • (1989) Ph.D. dissertation
    • Low, K.K.1
  • 15
    • 0015483450 scopus 로고
    • Practical least pth optimization of networks
    • Dec.
    • J. W. Bandler and C. Charalambous, “Practical least pth optimization of networks,” IEEE Trans. Microwave Theory Tech., vol. MTT-20, pp. 834–840, Dec. 1972.
    • (1972) IEEE Trans. Microwave Theory Tech. , vol.MTT-20 , pp. 834-840
    • Bandler, J.W.1    Charalambous, C.2
  • 16
    • 0021425044 scopus 로고
    • An improved min-cut algorithm for partitioning VLSI networks
    • May
    • B. Krishnamurthy, “An improved min-cut algorithm for partitioning VLSI networks,” IEEE Trans. Comput., vol. C-33, pp. 438–446, May 1984.
    • (1984) IEEE Trans. Comput. , vol.C-33 , pp. 438-446
    • Krishnamurthy, B.1
  • 17
    • 85046457769 scopus 로고
    • A linear-time heuristic for improving network partitions
    • Dec.
    • C. M. Fiduccia and R. M. Mettheyses, “A linear-time heuristic for improving network partitions,” in Proc. 19th Design Automation Conf., Dec. 1982, pp. 175–181.
    • (1982) Proc. 19th Design Automation Conf. , pp. 175-181
    • Fiduccia, C.M.1    Mettheyses, R.M.2
  • 18
    • 0004043713 scopus 로고
    • Optimization Methods For Large-Scale Systems-With Applications
    • ed., New York: McGraw-Hill
    • D. A. Wismer, ed., Optimization Methods For Large-Scale Systems-With Applications. New York: McGraw-Hill, 1971.
    • (1971)
    • Wismer, D.A.1
  • 19
    • 0003540822 scopus 로고
    • Systems: Decomposition, Optimisation and Control
    • New York: Pergamon
    • M. G. Singh and A. Titli, Systems: Decomposition, Optimisation and Control. New York: Pergamon, 1978.
    • (1978)
    • Singh, M.G.1    Titli, A.2


* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.