메뉴 건너뛰기




Volumn 3, Issue 1-2, 1991, Pages 77-92

Control generation in the design of processor arrays

Author keywords

[No Author keywords available]

Indexed keywords

COMPUTER OPERATING SYSTEMS; COMPUTER PROGRAMMING--ALGORITHMS; CONTROL SYSTEMS;

EID: 0026171253     PISSN: 09225773     EISSN: 1573109X     Source Type: Journal    
DOI: 10.1007/BF00927836     Document Type: Article
Times cited : (28)

References (39)
  • 1
    • 84936307750 scopus 로고    scopus 로고
    • H. Kung, “Let's design algorithms for VLSI system,” in Proc. Caltech Conf. on VLSI, 1979, pp. 65–90.
  • 3
    • 84936326793 scopus 로고    scopus 로고
    • H. Kung and C. Leiserson, “Systolic arrays for VLSI,” in SIAM Sparse Matrix Proceedings, Philadelphia, 1978, pp. 245–282.
  • 4
    • 84936372482 scopus 로고    scopus 로고
    • U. Schwiegelshohn and L. Thiele, “One- and two-dimensional arrays for least squares problems,” in IEEE Conf. on Acoust. Speech Signal Processing, Dallas, 1987, pp. 791–794.
  • 7
    • 84936339695 scopus 로고    scopus 로고
    • L. Thiele, “Computational arrays for Jacobi algorithms,” in SVD and Signal Processing, North Holland Pub., 1988, pp. 369–383.
  • 8
    • 84936306356 scopus 로고    scopus 로고
    • L. Guibas, H. Kung, and C. Thompson, “Direct VLSI implementation of combinatorial algorithms,” in Proc. Conf. on VLSI: Architecture, Design and Fabrication, 1979, pp. 509–525.
  • 9
    • 84936372876 scopus 로고    scopus 로고
    • M. Huber, “A systolic processor chip dedicated to the shortest path problem,” in Proceedings of COMPEURO 87, Hamburg, 1987, pp. 500–501.
  • 10
    • 84936358612 scopus 로고    scopus 로고
    • U. Schwiegelshohn and L. Thiele, “A systolic array for the assignment problem,”IEEE Trans. Computers, 1988, pp. 1422–1425.
  • 11
    • 84936344144 scopus 로고    scopus 로고
    • S.K. Rao and T. Kailath, “Systematic design of special purpose processor arrays,”Proceedings of the IEEE, 1987.
  • 12
    • 84936343629 scopus 로고    scopus 로고
    • P. Quinton, “Automatic synthesis of systolic arrays from uniform recurrent equations,” in The IEEE/ACM 11th Annual Int'l Symp. on Computer Architecture, Ann Arbor, MI, 1984, pp. 208–214.
  • 13
    • 84936316154 scopus 로고    scopus 로고
    • S.K. Rao, Regular iterative algorithms and their implementations on processor arrays. PhD thesis, Stanford University, 1985.
  • 14
    • 84936303720 scopus 로고    scopus 로고
    • W.L. Miranker and A. Winkler, “Space-time representation of computational structures,”Computing, 1984, pp. 93–114.
  • 15
    • 84936317605 scopus 로고    scopus 로고
    • D.I. Moldovan, “On the design of algorthms for VLSI systolic arrays,”Proceedings of the IEEE, 1983, pp. 113–120.
  • 16
    • 84936331326 scopus 로고    scopus 로고
    • J. Annevelink and P. Dewilde, “HIFI: A functional design system for VLSI processing arrays,” in Proc. Int'l Conf. on Systolic Arrays, San Diego, 1988, pp. 433–452.
  • 17
    • 84936351955 scopus 로고    scopus 로고
    • L. Thiele, “On the hierarchical design of VLSI processor arrays,” in IEEE Symp. on Circuits and Systems, Helsinki, 1988, pp. 2517–2520.
  • 18
    • 84936333171 scopus 로고    scopus 로고
    • A. Benani and Y. Robert, “Spacetime-minimal systolic arrays for Gaussian elimination and the Algebraic Path Problem,” Report from the Ecole Normale Superieure de Lyon, vol. 9, 1990.
  • 20
    • 84936316511 scopus 로고    scopus 로고
    • M. Chen and K. Yao, “On realization and implementation of Kalman filtering systolic arrays,” in Proceedings of John Hopkins Workshop, 1987.
  • 22
    • 84936336682 scopus 로고    scopus 로고
    • H. Nelis, E.F. Deprettere, and J. Bu, “Automatic design and partitioning of algorithms for VLSI systolic/wavefront arrays,” in Proc. SPIE Conference, San Diego, 1987.
  • 23
    • 84936345353 scopus 로고    scopus 로고
    • Y.Wong and J.M. Delosme, “Broadcase removal in systolic algorithms,” in Proc. of Int'l Conf. on Systolic Arrays, San Diego, 1988, pp. 403–412.
  • 26
    • 84936359451 scopus 로고    scopus 로고
    • L. Thiele, “On the design of piecewise regular processor arrays,” in Proc. IEEE Symp. on Circuits and Systems, Portland, 1989, pp. 2239–2242.
  • 29
    • 84936354283 scopus 로고    scopus 로고
    • C.H. Chu, “A Model for an Intelligent Operating System for Executing Image Understanding Tasks on a Reconfigurable Architecture,”Journal of Parallel and Distributed Computing, vol. 6, 89, pp. 598–622.
  • 30
    • 0025235180 scopus 로고
    • A Taxonomy of Reconfiguration Techniques for Fault-Tolerant Processor Arrays
    • (1990) Computer , vol.23 , pp. 55-69
    • Chean, M.1    Fortes, J.2
  • 31
    • 84936352258 scopus 로고    scopus 로고
    • P. Frison, D. Lavenier, H. Leverge, and P. Quinton, “MICS-MACS: A VLSI Programmable Systolic Architecture,” in Proc. Int. Conf. Systolic Arrays, 1989, pp. 146–155.
  • 32
    • 84936311007 scopus 로고    scopus 로고
    • O. Menzilcioglu, H.T. Kung, and S.W. Song, “A Highly Configurable Architecture for Systolic Arrays of Powerful Processors,” in Proc. Int. Conf. Systolic Arrays, 1989, pp. 165–165.
  • 33
    • 84936336860 scopus 로고    scopus 로고
    • L. Snyder, “Introduction to the Configurable, Highly Parallel Computer,”Computer, 1982, pp. 47–56.
  • 35
    • 84936362183 scopus 로고    scopus 로고
    • S. Rajopadhye and R. Fujimoto, “Systolic array synthesis by static analysis of program dependencies,” in Proc. of Parallel Architectures and Languages Europe J. Bakker, A. Nijman, and P. Treleaven, eds., Springer Verlag, 1987, pp. 295–310.
  • 38
    • 84936329893 scopus 로고    scopus 로고
    • M. Huber, J. Teich, and L. Thiele, “Design of configurable processor arrays (invited paper),“ in Proc. IEEE Int. Symp. Circuits and Systems, New Orleans, 1990, pp. 970–973.


* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.